170 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.8.72 EXP_MASKERR – PCI Express Mask Error (D2:F0)
Address Offset: 144 – 147h
Access: RO, R/W
Size: 32 Bits
Default: 0000_E000h
This register masks individual non-PCI Express unit errors from being reported. They are still
logged when masked, but only in the PCI Express Unit Error register. They will not be logged in
either the local (EXP_FERR/EXP_NERR) or global FERR/NERR registers. The lowest nibble of
this register is for the Hot-Swap Controller, and thus not applicable to this device.
5 0b
R/WC
DLLP Timeout Error. DLLP flow control traffic is not received within the expected
time. This bit is not set for time-outs related to ACK or NAK. This bit is sticky
through reset.
0 = Software clears this bit by writing a ‘1’ to the bit position.
1 = DLLP timeout error occurred.
4:3 00b Reserved
2 0b
R/WC
SMB Clock Low Timeout (SMBCLTO). This bit is sticky through reset.
0 = Software clears this bit by writing a ‘1’ to the bit position.
1 = SMB CLK low greater than 25ms.
1 0b
R/WC
Unexpected NAK on SMB (UESMBN). This bit is sticky through reset.
0 = Software clears this bit by writing a ‘1’ to the bit position.
1 = Unexpected NAK on SMB detected.
0 0b
R/WC
SMB Lost Bus Arbitration (SMBLA). (Correctable) This bit is sticky through
reset.
0 = Software clears this bit by writing a ‘1’ to the bit position.
1 = SMB lost bus arbitration.
Bit Field
Default &
Access
Description
Bit Field
Default &
Access
Description
31:16 0000h Reserved
15 1b
R/W
Upstream Posted Queue Overflow Mask. Defaults to masked, normally
reported through PCI Express receive overflow status bit. This bit is sticky through
reset.
0 = Enable upstream posted queue overflow reporting.
1 = Disable upstream posted queue overflow reporting.
14 1b
R/W
Upstream Non-Posted Queue Overflow Mask. Defaults to masked, normally
reported through PCI Express receive overflow status bit. This bit is sticky through
reset.
0 = Enable upstream non-posted queue overflow reporting.
1 = Disable upstream non-posted queue overflow reporting.
13 1b
R/W
Upstream Completion Queue Overflow Mask. Defaults to masked, normally
reported through PCI Express receive overflow status bit. This bit is sticky through
reset.
0 = Enable upstream completion queue overflow reporting.
1 = Disable upstream completion queue overflow reporting.
12 0b
R/W
LLE Protocol Error Mask. This bit is sticky through reset.
0 = Enable LLE protocol error reporting.
1 = Disable LLE protocol error reporting.
