Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 169
Register Descriptions
14 0b
R/WC
Upstream Non-Posted Queue Overflow Status. This bit is one of the
components of the Receiver Overflow Status bit in the UNCERRSTS register.
Even though this bit can be set, it is only reported through the receiver overflow
bit in the UNCERRSTS register. The setting of this bit will never be logged in the
local FERR/NERR registers or subsequently the global FERR/NERR registers,
nor will it cause a SCI/SMI/SERR or MCERR message. At most, when the report
mask is disabled, it could affect the unit error pointer. This functionality is provided
as an aid to debug. This bit is sticky through reset.
0 = Software clears this bit by writing a ‘1’ to the bit position.
1 = Overflow occurred for the non-posted header queues.
13 0b
R/WC
Upstream Completion Queue Overflow Status. Even though this bit can be set,
it is only reported through the receiver overflow bit in the UNCERRSTS register.
The setting of this bit will never be logged in the local FERR/NERR registers or
subsequently the global FERR/NERR registers, nor will it cause a SCI/SMI/SERR
or MCERR message. This functionality is provided as an aid to debug. This bit is
sticky through reset.
0 = Software clears this bit by writing a ‘1’ to the bit position.
1 = Overflow occurred for one of the completion header or data queues.
12 0b
R/WC
LLE Protocol Error. This bit is set when the transaction layer detects a protocol
error on the receiver interface from the LLE. Such an event should cause
retraining eventually, but not necessarily immediately. The transaction with a
problem will be dropped. This bit is sticky through reset.
0 = Software clears this bit by writing a ‘1’ to the bit position.
1 = Transaction layer detected a protocol error on the receiver interface from the
LLE
11 0b
R/WC
Link Down Error. This bit is set when the link transition from DL_UP to
DL_DOWN. This error will not be set if any of the BCTRL[6] (Secondary Bus
Reset, HSILNKCTL[5] (Link Disabled), or VSCMD1[1] (Loopback Enable) bits are
set. All of these would be SW initiated Link Down events which should not be
considered errors.
0 = Software clears this bit by writing a ‘1’ to the bit position.
1 = Set when the link transitions from DL_UP to DL_DOWN.
10 0b
R/WC
Downstream Data Queue Parity Error. This bit is sticky through reset.
0 = Software clears this bit by writing a ‘1’ to the bit position.
1 = Parity error occurred in the downstream data queue.
9 0b
R/WC
LUT Parity Error. Setting this bit indicates the logic is now lost and no transfers
can be processed. The link is forced into retraining. When this error occurs, it will
most likely be reported as multiple errors, since the error will be reported as long
as the row with the error is accessed. This bit is sticky through reset.
0 = Software clears this bit by writing a ‘1’ to the bit position.
1 = Parity error occurred in the Lookup Table.
8 0b
R/WC
LLRB Data Parity Error. This error can only occur during a retry. This bit is sticky
through reset.
0 = Software clears this bit by writing a ‘1’ to the bit position.
1 = Data Parity error occurred in the Link Level Retry Buffer.
7 0b
R/WC
LLRB Header Parity Error. The current transaction will be terminated as marked
as bad. No further transfers will be completed. This error can only occur during a
retry. This bit is sticky through reset.
0 = Software clears this bit by writing a ‘1’ to the bit position.
1 = LLRB header parity error detected. Fatal.
6 0b
R/WC
LLRB Control Parity Error. Since the pointer information is somehow lost or
corrupted, no further data transfers can be completed. This error can only occur
during a retry. This bit is sticky through reset.
0 = Software clears this bit by writing a ‘1’ to the bit position.
1 = LLRB control parity error detected. Fatal.
Bit Field
Default &
Access
Description
