168 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.8.71 EXP_UNITERR – PCI Express Unit Error Status (D2:F0)
Address Offset: 140 – 143h
Access: RO, R/WC
Size: 32 Bits
Default: 0000_0000h
This register is specific to theMCH. It captures the non-PCI Express unit errors (those beyond the
scope of the bus specification). The unit error mechanism is parallel to that used by “compatible”
error registers and masks, but cannot feed back into standard registers because that would confuse
standardized error handling software (which would not understand the extracurricular error bits).
Escalation is controlled via the EXP_ERRDOCMD register (D2:F0:140-143h) for both standard
and MCH-specific error types. Uncorrectable fatal errors feed into the fatal reporting select,
uncorrectable non-fatal errors feed into the non-fatal reporting select, and correctable errors feed
into the correctable reporting select. The lower nibble is for HPC related errors. These bits are
sticky through reset.
Bit Field
Default &
Access
Description
31:16 0000h
RO
Uncorrectable Error Source ID. Requestor ID of the source when an
uncorrectable error (fatal or nonfatal) is received, and the First Uncorrectable
Error Detected bit is not already set. Since this ID could be for an internally
detected error or from a message received from the other end of the link, in the
event of errors detected in the same clock, priority will be given to the error
received from the link, and that ID is what will be logged. These bits are sticky
through reset.
15:0 0000h
RO
Correctable Error Source ID. Requestor ID of the source when an correctable
error is received, and the First Correctable Error Detected bit is not already set.
Since this ID could be for an internally detected error or from a message received
from the other end of the link, in the event of errors detected in the same clock,
priority will be given to the error received from the link, and that ID is what will be
logged. These bits are sticky through reset.
Bit Field
Default &
Access
Description
31:16 0000h Reserved
15 0b
R/WC
Upstream Posted Queue Overflow Status. This bit is one of the components of
the Receiver Overflow Status bit in the UNCERRSTS register. Even though this
bit can be set, it is only reported through the receiver overflow bit in the
UNCERRSTS register. The setting of this bit will never be logged in the local
FERR/NERR registers or subsequently the global FERR/NERR registers, nor will
it cause a SCI/SMI/SERR or MCERR message. At most, when the report mask is
disabled, it could affect the unit error pointer. This functionality is provided as an
aid to debug. This bit is sticky through reset.
0 = Software clears this bit by writing a ‘1’ to the bit position.
1 = Overflow occurred for one of the posted header or data queues.
