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QGE7520MC-SL8EE

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型号: QGE7520MC-SL8EE
PDF文件:
  • QGE7520MC-SL8EE PDF文件
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功能描述: Intel® E7520 Memory Controller Hub (MCH)
PDF文件大小: 2594.09 Kbytes
PDF页数: 共282页
制造商: INTEL[Intel Corporation]
制造商LOGO: INTEL[Intel Corporation] LOGO
制造商网址: http://www.intel.com
捡单宝QGE7520MC-SL8EE
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120%
Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 167
Register Descriptions
3.8.70 EXP_ERRSID – PCI Express Error Source ID (D2:F0)
Address Offset: 134 – 137h
Access: RO
Size: 32 Bits
Default: 0000_0000h
This register reports the source (Requestor ID) of the first correctable and uncorrectable (fatal or
nonfatal) errors reported in the Root Error Status register. These bits are sticky through reset.
5 0b
R/WC
Non-Fatal Error Messages Detected. This bit is used by error handling software
to determine whether non-fatal errors are outstanding in the hierarchy. In
hardware, this bit along with bits 4 and 2 is used to clear non-fatal error
escalation. This bit is sticky through reset.
0 = Software clears this bit by writing a ‘1’ to the bit location.
1 = Non-fatal error message detected.
4 0b
R/WC
First Uncorrectable Fatal Flag. This bit is sticky through reset.
0 = First uncorrectable error is non-fatal.
1 = First uncorrectable error is fatal.
3 0b
R/WC
Multiple Uncorrectable Errors Detected. In the unlikely event of two first errors
occurring during the same clock period, only the first uncorrectable error message
bit will be set. It will take an error to occur in a subsequent clock to set this bit.
This bit is sticky through reset.
0 = Software clears this bit by writing a ‘1’ to the bit location.
1 = Set when either a fatal or nonfatal error is received, and the First
Uncorrectable Error Detected bit is already set. This indicates that one or
more message Requestor IDs were lost.
2 0b
R/WC
First Uncorrectable Error Detected. This bit is sticky through reset.
0 = Software clears this bit by writing a ‘1’ to the bit location.
1 = Set when the first fatal or nonfatal error is received.
1 0b
R/WC
Multiple Correctable Errors Detected. In the unlikely event of two first errors
occurring during the same clock period, only the first correctable error message
bit will be set. It will take an error to occur in a subsequent clock to set this bit.
This bit is sticky through reset.
0 = Software clears this bit by writing a ‘1’ to the bit location.
1 = Set when a correctable error is received, and the First Correctable Error
Detected bit is already set. This indicates that one or more message
Requestor IDs were lost.
0 0b
R/WC
First Correctable Error Detected. This bit is sticky through reset.
0 = Software clears this bit by writing a ‘1’ to the bit location.
1 = Set when the first correctable error is received.
Bit Field
Default &
Access
Description
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