166 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.8.69 EXP_RPERRMSTS – PCI Express Root Port Error Message
Status (D2:F0)
Address Offset: 130 – 133h
Access: RO, R/WC
Size: 32 Bits
Default: 0000_0000h
This register reports the status of errors received by the root complex. Each correctable and
uncorrectable (nonfatal and fatal) error source has a First Error bit and a Next Error bit. When an
error is received by the root complex, the associated First Error bit is set and the Requestor ID is
logged in the Error Source Identification register. Software may clear an error status bit by writing
a ‘1’ to the bit location. If software does not clear the first reported error before another error is
received, the Next Error status bit will be set, but the Requestor ID of the subsequent error message
is discarded.
Bit Field
Default &
Access
Description
31:3 0 Reserved
2 0b
R/W
Fatal Error Interrupt Enable. Enables the generation of an interrupt when a fatal
error is reported by any of the devices in the hierarchy associated with this Root
Port. This bit is sticky through reset.
0 = Disable interrupt generation on fatal error.
1 = Enable interrupt generation on fatal error.
1 0b
R/W
Nonfatal Error Interrupt Enable. Enables the generation of an interrupt when an
nonfatal error is reported by any of the devices in the hierarchy associated with
this Root Port. This bit is sticky through reset.
0 = Disable interrupt generation on nonfatal error.
1 = Enable interrupt generation on nonfatal error.
0 0b Correctable Error Interrupt Enable. Enables the generation of an interrupt when
a correctable error is reported by any of the devices in the hierarchy associated
with this Root Port. This bit is sticky through reset.
0 = Disable interrupt generation on correctable error.
1 = Enable interrupt generation on correctable error.
Bit Field
Default &
Access
Description
31:27 0h
RO
Advanced Error Interrupt Message Number. If this function has been allocated
more than one MSI interrupt number, this field will reflect the offset between the
base Message Data and the MSI Message that is generated when any of the
status bits of this capability are set.
26:7 0_0000h Reserved
6 0b
R/WC
Fatal Error Messages Detected. This bit is used by error handling software to
determine whether fatal errors are outstanding in the hierarchy. In hardware, this
bit along with bits 4 and 2 is used to clear fatal error escalation. This bit is sticky
through reset.
0 = Software clears this bit by writing a ‘1’ to the bit location.
1 = Fatal error message detected.
