Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 165
Register Descriptions
3.8.66 EXP_HDRLOG2 – PCI Express Header Log DW2 (D2:F0)
Address Offset: 124 – 127h
Access: RO
Size: 32 Bits
Default: 0000_0000h
The function of the Header Log registers is described in Section 3.8.64 on page 3-164. Header Log
DW2 contains the third 32 bits of the header. Byte 8 of the header is located in byte 3 of the Header
Log register 2, byte 9 of the header is in byte 2 of the Header Log register 2 and so forth. These bits
are sticky through reset.
3.8.67 EXP_HDRLOG3 – PCI Express Header Log DW3 (D2:F0)
Address Offset: 128 – 12Bh
Access: RO
Size: 32 Bits
Default: 0000_0000h
The function of the Header Log registers is described in Section 3.8.64 on page 3-164. Header Log
DW3 contains the fourth 32 bits of the header. For 16-byte headers, byte 12 of the header is located
in byte 3 of the Header Log register 3, byte 13 of the header is in byte 2 of the Header Log register
3 and so forth. For 12 byte headers, values in this register are undefined. These bits are sticky
through reset.
3.8.68 EXP_RPERRCMD – PCI Express Root Port Error Command
(D2:F0)
Address Offset: 12C – 12Fh
Access: R/W
Size: 32 Bits
Default: 0000_0000h
This register controls the generation of interrupts (beyond the basic root complex capability to
generate system errors) upon detection of errors. System error generation in response to PCI
Express error messages may be turned off by system software using the PCI Express Capability
Structure when advanced error reporting via interrupts is enabled.
Bit Field
Default &
Access
Description
31:0 0000_0000h
RO
Header Log 2
Bit Field
Default &
Access
Description
31:0 0000_0000h
RO
Header Log 3
