164 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.8.64 EXP_HDRLOG0 – PCI Express Header Log DW0 (D2:F0)
Address Offset: 11C – 11Fh
Access: RO
Size: 32 Bits
Default: 0000_0000h
This register contains the first 32 bits of the header log locked down when the first uncorrectable
error occurs that saves the header. To rearm this register all reported uncorrectable errors must be
cleared from the register. Software after clearing the errors must read the register again to ensure
that it is indeed cleared. If it finds that another error occurred, it can not rely on the pointer or
header, unless it detects that the error pointer changed from the last time it was read for the
previous error. Byte 0 of the header is located in byte 3 of the Header Log register 0, byte 1 of the
header is in byte 2 of the Header Log register 0 and so forth. For 12 byte headers, only the first
three of the four Header Log registers are used, and values in HDRLOG3 are undefined. These bits
are sticky through reset.
3.8.65 EXP_HDRLOG1 – PCI Express Header Log DW1 (D2:F0)
Address Offset: 120 – 123h
Access: RO
Size: 32 Bits
Default: 0000_0000h
The function of the Header Log registers is described in Section 3.8.64 on page 3-164. Header Log
DW1 contains the second 32 bits of the header. Byte 4 of the header is located in byte 3 of the
Header Log register 1, byte 5 of the header is in byte 2 of the Header Log register 1 and so forth.
These bits are sticky through reset.
5 0b
RO
ECRC Generation Capable. Not supported on the MCH.
4:0 00h
RO
First Error Pointer. Identifies the bit position of the first error reported in the
Uncorrectable Error Status register. However, if a subsequent Uncorrectable Error
occurs with a higher severity, this field will be over-written with the bit position of
the subsequent error status bit. In the event of simultaneous errors, the pointer
indicates the least significant bit of the group. This bit is sticky through system
reset.
Bit Field
Default &
Access
Description
Bit Field
Default &
Access
Description
31:0 0000_0000h
RO
Header Log 0
Bit Field
Default &
Access
Description
31:0 0000_0000h
RO
Header Log 1
