Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 161
Register Descriptions
The Uncorrectable Error Severity register controls whether an individual error is reported as a
nonfatal or fatal error. An error is reported as fatal when the corresponding error bit in the severity
register is set. If the bit is cleared, the corresponding error is considered nonfatal. These bits are
sticky through reset.
3.8.61 EXP_CORERRSTS – PCI Express Correctable Error Status
(D2:F0)
Address Offset: 110 – 113h
Access: R/WC
Size: 32 Bits
Default: 0000_0000h
Bit Field
Default &
Access
Description
31:21 0 Reserved
20 0b
R/W
Unsupported Request Error Severity.
0 = Nonfatal
1 = Fatal
19 0b
RO
ECRC Error Severity. OPTIONAL. Not implemented.
18 1b
R/W
Malformed TLP Severity.
0 = Nonfatal
1 = Fatal
17 1b
R/W
Receiver Overflow Severity. OPTIONAL
0 = Nonfatal
1 = Fatal
16 0b
R/W
Unexpected Completion Severity.
0 = Nonfatal
1 = Fatal
15 0b
R/W
Completer Abort Severity. OPTIONAL
0 = Nonfatal
1 = Fatal
14 0b
R/W
Completion Timeout Severity.
0 = Nonfatal
1 = Fatal
13 1b
R/W
Flow Control Protocol Error Severity. OPTIONAL
0 = Nonfatal
1 = Fatal (Default
12 0b
R/W
Poisoned TLP Severity.
0 = Nonfatal
1 = Fatal
11:5 0 Reserved
4 1b
R/W
Data Link Protocol Error Severity.
0 = Nonfatal
1 = Fatal
3:1 0 Reserved
0 0b
RO
Training Error Severity. OPTIONAL. Not implemented.
0 = Nonfatal
1 = Fatal
