Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 159
Register Descriptions
3.8.59 EXP_UNCERRMSK – PCI Express Uncorrectable Error
Mask (D2:F0)
Address Offset: 108 – 10Bh
Access: RO, R/W
Size: 32 Bits
Default: 0000_0000h
The Uncorrectable Error Mask register controls reporting of individual errors by device to the PCI
Express Root Complex via a PCI Express error message. A masked error (respective bit set in mask
register) is not reported to the PCI Express Root Complex by an individual device. However,
16 0b
R/WC
Unexpected Completion Status. This bit will be set when the device receives a
completion which does not correspond to any of the outstanding requests issued
by that device. This error, if the first uncorrectable error, will load the header log.
This bit is sticky through reset.
0 = Cleared by writing a ‘1’ to the bit location.
1 = Unexpected Completion detected.
15 0b
R/WC
Completer Abort Status. OPTIONAL If a request received violates the specific
programming model of this device, but is otherwise legal, this bit will be set. This
error, if the first uncorrectable error, will load the header log. This bit is sticky
through reset.
0 = Cleared by writing a ‘1’ to the bit location.
1 = Completer Abort detected.
14 0b
R/WC
Completion Timeout Status. The Completion Timeout timer will expire if a
Request is not completed within 16 ms, but must not expire earlier than 50 us.
When the timer expires, this bit will be set. This bit is sticky through reset.
0 = Cleared by writing a ‘1’ to the bit location.
1 = Completion timeout detected.
13 0b
R/WC
Flow Control Protocol Error Status. OPTIONAL The MCH asserts this bit for
one of two conditions:
1. An FC update has been received which describes header or data credits for P,
NP, or CPL which were originally advertised as infinite during initialization but
are now advertised with non-zero or non-infinite values.
2. The minimum number of credits is not being advertised. The MCH implements
this error bit, but only implements checking for conditions 1 and 3.
This bit is sticky through reset.
0 = Cleared by writing a ‘1’ to the bit location.
1 = Flow Control Protocol Error detected.
12 0b
R/WC
Poisoned TLP Status. This bit when set indicates that some portion of the TLP
data payload was corrupt. This error, if the first uncorrectable error, will load the
header log. This bit is sticky through reset.
0 = Cleared by writing a ‘1’ to the bit location.
1 = Poisoned TLP detected.
11:5 0 Reserved
4 0b
R/WC
Data Link Protocol Error Status. This bit is set when an ACK/NAK received
does not specify the sequence number of an unacknowledged TLP, or of the most
recently acknowledged TLP. This bit is sticky through reset.
0 = Cleared by writing a ‘1’ to the bit location.
1 = Data Link Protocol Error detected.
3:1 0 Reserved
0 0b
RO
Training Error Status. OPTIONAL. Not implemented.
Bit Field
Default &
Access
Description
