Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 153
Register Descriptions
3.8.49 EXP_LNKSTS – PCI Express Link Status (D2:F0)
Address Offset: 76 – 77h
Access: RO
Size: 16 Bits
Default: 1001h
This register provides information about PCI Express link-specific parameters.
3 0b
RO
Read Completion Boundary. “RCB” capability of 64B.
2 0b Reserved
1:0 00b
R/W
Active State Link PM Control. Controls the level of active state power
management supported on the associated PCI Express link.
00 = Disabled
01 = Reserved
10 = Reserved
11 = Reserved
Bit Field
Default &
Access
Description
Bit Field
Default &
Access
Description
15:13 000b Reserved
12 1b
RO
Slot Clock Configuration. Indicates whether or not the component uses the
same physical reference clock that the platform provides on the connector.
0 = The component in the slot uses an independent reference clock, irrespective
of the presence of a reference on the connector.
1 = The component in the slot uses the same physical reference clock provided
on the connector.
11 0b
RO
Link Training. Indicates link training in progress (Physical Layer LTSSM in
Configuration or Recovery state); hardware clears this bit once Link Training is
successfully trained to the L0 state
0 = Cleared by hardware once link training is complete.
1 = Set by hardware when link training is in progress.
10 0b
RO
Link Training Error.
0 = No Link Training Error
1 = Link Training Error occurred during transition from config or recovery to
detect
9:4 000000b
RO
Negotiated Width. All other values are Reserved.
000001b = x1
000100b = x4
001000b = x8
3:0 1h
RO
Link Speed. The link speed is 2.5 GB/s.
