150 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.8.46 EXP_DEVSTS – PCI Express Device Status (D2:F0)
Address Offset: 6E – 6Fh
Access: RO, R/WC
Size: 16 Bits
Default: 0000h
This register provides information about PCI Express device-specific parameters.
1 0b
R/W
Non-Fatal Error Reporting Enable. This bit controls the reporting of nonfatal
errors. Note that the reporting of nonfatal errors is internal to the root. No external
ERR_NONFATAL message is generated. PCICMD[SERRE] when set can also
enable reporting of both internal and external errors to be reported.
0 = Disable nonfatal error reporting
1 = Enable nonfatal error reporting
0 0b
R/W
Correctable Error Reporting Enable. This bit controls the reporting of
correctable errors. Note that the reporting of correctable errors is internal to the
root. No external ERR_CORR message is generated.
0 = Disable correctable error reporting
1 = Enable correctable error reporting
Bit Field
Default &
Access
Description
Bit Field
Default &
Access
Description
15:6 0 Reserved
5 0b
RO
Transactions Pending. Indicates that the device has transactions pending.
0 = Cleared by hardware only when all pending transactions (including
completions for any outstanding non-posted requests on any used virtual
channel) have been completed.
1 = Set by hardware to indicate that transactions are pending (including
completions for any outstanding non-posted requests for all used Traffic
Classes).
4 0b
RO
AUX Power Detected. Not Applicable.
3 0b
R/WC
Unsupported Request Detected. Indicates that an Unsupported Request has
been detected. This bit is set upon Unsupported Request detection regardless of
whether or not error reporting is enabled in the Device Control register. Software
clears this bit by writing a ‘1’ to the bit location.
0 = No Unsupported Request detected
1 = Unsupported Request detected
2 0b
R/WC
Fatal Error Detected. Indicates that a fatal error has been detected. This bit is
set upon fatal error detection regardless of whether or not error reporting is
enabled in the Device Control register. Software clears this bit by writing a ‘1’ to
the bit location.
0 = No fatal error detected
1 = Fatal error detected