Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 15
Intel
®
E7520 MCH Feature Overview
Supports Intel
®
Xeon™ Processors with 800 MHz
system bus
—800 MHz system bus 2X address, 4X data)
—Symmetric Multiprocessing Protocol (SMP) for
up to two processors at 800 MHz
—Parity protection on address, data, request, and
response signals
—Supports Hyper-Threading Technology
—Dynamic Bus Inversion (DBI)
—36-bit host interface addressing support
—12-deep in-order queue
—AGTL+ technology with on-die termination
Memory System
—Support for 128 Mb (DDR266 and DDR333
only), 256 Mb, 512 Mb, and 1 Gb DRAM
densities
—Up to two registered memory DDR channels
operating in lock-step at DDR266, DDR333 or
DDR2-400
—Data bandwidth per channel of 2.13 GB/s
(DDR266), 2.67 GB/s (DDR333) or 3.2 GB/s
(DDR2-400)
—Maximum memory size 32 GB (DDR266) or 16
GB (DDR333 and DDR2-400)
—Hardware memory initialization
Integrated four-channel DMA engine with
IOxAPIC functionality
High Speed Serial PCI Express Interface
—Three x8 PCI Express interfaces. Each of these
interfaces can be configured as two independent
x4 interfaces.
—32-bit CRC and hardware link-level retry
—Compatible with PCI Express Interface
Specification, Rev 1.0a
—High bandwidth connection of 4 GB/s per x8
port to I/O processor, PCI-X, Ethernet, or
Infiniband* Technology bridge devices
—Supports 36-bit addressing using 64-bit
semantics
—Support for peer segment destination write
traffic between PCI Express ports
—Support for non-snooped traffic to memory
—Support for remote boot
—Support for link active-state and ACPI power
management
Hub Interface to Intel
®
I/O Controller Hub
—266 MB/s interface to Intel
®
82801ER ICH5R
or 6300ESB ICH via HI 1.5
—Parity protected
—Support for differentiated, high priority requests
—32-bit downstream addressing
—64-bit upstream addressing (full DAC support)
truncated to 36 bits internally
—Power management messaging
RASUM
—Support for automatic read retry on
uncorrectable errors
—Support for RAS fail-over to an on-line spare
DIMM
—Support for memory mirroring
—Hardware periodic memory scrubbing,
including demand scrub support
—Full access to configuration registers via SMBus
and IEEE 1149.1 JTAG ports
—Support for Intel
®
x4 Single Device Data
Correction (x4 SDDC)
—Support for standard SEC-DED (72, 64) ECC
on each channel when x4 SDDC technology is
disabled
Package
—1077-ball, 42.5 mm, FC-BGA package