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QGE7520MC-SL8EE

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型号: QGE7520MC-SL8EE
PDF文件:
  • QGE7520MC-SL8EE PDF文件
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功能描述: Intel® E7520 Memory Controller Hub (MCH)
PDF文件大小: 2594.09 Kbytes
PDF页数: 共282页
制造商: INTEL[Intel Corporation]
制造商LOGO: INTEL[Intel Corporation] LOGO
制造商网址: http://www.intel.com
捡单宝QGE7520MC-SL8EE
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120%
Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 149
Register Descriptions
Bit Field
Default &
Access
Description
15 0b Reserved
14:12 000b
R/W
Max Read Request Size. The maximum Read Request size for the device as a
requester. The MCH will not generate read requests with size exceeding the set
value.
000b = 128B 100b = 2KB
001b = 256B 101b = 4KB
010b = 512B 110b = Reserved
011b = 1KB 111b = Reserved
The MCH will break cache-line (64B) reads destined for the I/O subsystem into
pairs of aligned sequential 32B reads. Because of this, the read request size is
not limited by the value in this register.
11 0b
RO
Enable No Snoop. Software override on usage of the “No Snoop” attribute.The
MCH never issues transactions with this attribute set.
10 0b
RO
AUX Power PM Enable. Not Applicable.
9 0b
RO
Phantom Functions Enable. Not Applicable to a Root port.
8 0b
RO
Extended Tag Field Enable. Not Applicable to a Root port.
7:5 000b
R/W
Max Payload Size. The maximum TLP payload size for the device. As a receiver,
the device must handle TLPs as large as the set value; as transmitter, the device
must not generate TLPs exceeding the set value. Permissible values that can be
programmed are indicated by the max_payload_size supported in the device
capabilities register. Defined encodings for this field are:
000b = 128B 100b = 2KB
001b = 256B 101b = 4KB
010b = 512B 110b = Reserved
011b = 1KB 111b = Reserved
4 0b
RO
ERO Enable Relaxed Ordering. Permits the device to set the Relaxed Ordering
bit in the attributes field of transactions it issues that do not require strong write
ordering. Writes cannot be performed on this bit field.
MCH sends TLPs with ERO attribute set as follows:
For Messages, I/O space, memory space & CFG space transactions, ERO = 0
For Peer-to-Peer transactions, ERO received from the transaction requester will
be transmitted to the target as is.
For Completions packets, ERO from the original request will be copied into
completion packets.
3 0b
R/W
Unsupported Request Reporting Enable. Enables/Disables reporting of
Unsupported Request errors. Note that the reporting of error messages
(ERR_CORR, ERR_NONFATAL, ERR_FATAL) is controlled exclusively by the
Root Port Command register.
0 = Disable reporting of Unsupported Request errors
1 = Enable reporting of Unsupported Request errors
2 0b
R/W
Fatal Error Reporting Enable. This bit controls the reporting of fatal errors. Note
that the reporting of fatal errors is internal to the root. No external ERR_FATAL
message is generated. PCICMD[SERRE] when set can also enable reporting of
both internal and external errors to be reported.
0 = Disable fatal error reporting
1 = Enable fatal error reporting
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