148 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.8.44 EXP_DEVCAP – PCI Express Device Capabilities (D2:F0)
Address Offset: 68 – 6Bh
Access: RO
Size: 32 Bits
Default: 0002_8001h
This register identifies the device capabilities for PCI Express.
3.8.45 EXP_DEVCTL – PCI Express Device Control (D2:F0)
Address Offset: 6C – 6Dh
Access: RO, R/W
Size: 16 Bits
Default: 0000h
This register details PCI Express device-specific parameters.
Bit Field
Default &
Access
Description
31:28 0h Reserved
27:26 00b
RO
Slot Power Limit Scale. Specifies the scale used for the Slot Power Limit value.
This value is set by the Set_Slot_Power_Limit message. This is not applicable to
root ports.
00 = 1.0x (25.5 – 255)
01 = 0.1x (2.55 – 25.5)
10 = 0.01x (0.255 – 2.55)
11 = 0.001x (0.0 – 0.255)
25:18 00h
RO
Slot Power Limit Value. In combination with the Slot Power Limit Scale value,
specifies the upper limit on power supplied by the slot. Power Limit (in watts) is
calculated by multiplying the value in this field by the value in the Slot Power Limit
Scale field. This is not applicable to root ports.
17:15 000b Reserved
14 0b
RO
Power Indicator Present. Not Applicable to a Root port.
13 0b
RO
Attention Indicator Present. Not Applicable to a Root port.
12 0b
RO
Attention Button Present. Not Applicable to a Root port.
11:9 000b
RO
Endpoint L1 Acceptable Latency. Not Applicable to a Root port.
8:6 000b
RO
Endpoint L0s Acceptable Latency. Not Applicable to a Root port.
5 0b
RO
Extended Tag Field Supported. 5 bits, as required for a Root port.
4:3 00b
RO
Phantom Functions Supported. Devices may implement all function numbers,
as required for Root ports.
2:0 001b
RO
Max Payload Size Supported. Maximum 256B inbound payload size supported.
The outbound payload size is restricted to a cacheline size (64B).
