Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 147
Register Descriptions
3.8.42 EXP_NPTR – PCI Express Next Capabilities Pointer (D2:F0)
Address Offset: 65h
Access: RO
Size: 8 Bits
Default: 00h
This register identifies the next PCI Express capability structure.
3.8.43 EXP_CAPA – PCI Express Features Capabilities (D2:F0)
Address Offset: 66 – 67h
Access: RO, R/WO
Size: 16 Bits
Default: 0041h
This register identifies PCI Express device type and associated capabilities.
Bit Field
Default &
Access
Description
7:0 10h
RO
CAP_ID. Capability ID
10h = PCI Express capability structure
Bit Field
Default &
Access
Description
7:0 00h
RO
Next Capability Pointer. Indicates there are no additional capability structures.
Bit Field
Default &
Access
Description
15:14 00b Reserved
13:9 00000b
RO
Interrupt Message Number. If the function is allocated more than one MSI
interrupt number, this field will contain the offset between the base Message Data
and the MSI Message that is generated when any of the status bits in either the
Slot Status or Root Port Status registers of this capability structure are set.
Hardware will update this field so that it is correct if the number of MSI Messages
assigned to the device (based on the setting of the Multiple Message Enable bits
in the MSI Capabilities register).
8 0b
R/WO
Slot Implemented. BIOS must set this bit at boot time if the PCI Express link
associated with this port is connected to a slot (as compared to being connected
to a motherboard component, or being disabled).
0 = Slot not implemented.
1 = Slot implemented.
7:4 4h
RO
Device/Port Type. Root Port Device
3:0 1h
RO
Capability Version. Compatible with the PCI Express Interface Specification,
Rev 1.0a.
