Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 145
Register Descriptions
these registers will be compatible to the default value of IOxAPIC. The software can reprogram
these registers to required values. The three registers are MSI Control register (MSICR), MSI
Address register (MSIAR) and MSI Data register (MSIDR). Depending on system requirement
each PCI Express channel can have a MSI block (provides better flexibility) or the PCI Express
controller as a whole will have one MSI block and all channels raise hardware interrupts to this
block.
The MSI Control register (MSICR) contains all the information related to the capability of PCI
Express MSI interrupts. Note that the MSICR register has been separated into its components,
MSIAPID, MSINPTR and MSICAPA for purposes of separate register definitions.
3.8.39 MSIAR – MSI Address Register for PCI Express (D2:F0)
Address Offset: 5C – 5Fh
Access: R/W
Size: 32 Bits
Default: FEE0_0000h
The MSI Address register (MSIAR) contains all the address related information to route MSI
interrupts.
Bit Field
Default &
Access
Description
15:8 00h Reserved
7 0b
RO
64-bit Address Capable. The PCI Express bridge is capable of 32-bit MSI
addressing.
6:4 0h
R/W
Multiple Message Enable. The software writes this field to indicate the number
of allocated messages, which is aligned to a power of two. When MSI is enabled,
the software will allocate at least one message to the device.
3:1 001b
RO
Multiple Message Capable. This device requires a capability for two messages.
0 0b
R/W
MSI Enable. Selects the method of interrupt delivery. Interrupts are generated for
one of five conditions as described in the descriptor control register for each
channel. If none of these five conditions are selected, software must poll for
status as no interrupts of either type will be generated.
0 = Legacy interrupts will be generated.
1 = Message Signaled Interrupts (MSI) will be generated.
Bit Field
Default &
Access
Description
31:20 FEEh
R/W
Address. Most significant 12-bits of 32-bit address.
19:12 00h
R/W
Destination ID. Should reflect the 63:56 bits of IOxAPIC redirection table entry.
The MCH may substitute other values in this field when redirecting to the System
Bus.
11:4 00h
R/W
Extended Destination ID. Reflects the 55:48 bits of IOxAPIC redirection table
entry.
3 0b
R/W
Redirection Hint.
0 = Direct. Message will be delivered to the agent listed in bits 19:12
1 = Redirect. Message will be delivered to an agent with a lower interrupt priority.
This can be derived from bits 10:8 in the Data Field.