144 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.8.35 PMDATA – Power Management Data (D2:F0)
Address Offset: 57h
Access: RO
Size: 8 Bits
Default: 00h
This register identifies the data read based on the data select. This register is not supported in the
MCH and is reserved.
3.8.36 MSICAPID – MSI Capabilities Structure (D2:F0)
Address Offset: 58h
Access: RO
Size: 8 Bits
Default: 05h
This register identifies the MSI capability structure.
3.8.37 MSINPTR – MSI Next Capabilities Pointer (D2:F0)
Address Offset: 59h
Access: RO
Size: 8 Bits
Default: 64h
This register points to the next structure.
3.8.38 MSICAPA – MSI Capabilities (D2:F0)
Address Offset: 5A – 5Bh
Access: RO, R/W
Size: 16 Bits
Default: 0002h
The PCI Express controller generates upstream interrupt message using MSI to the processor,
bypassing IOxAPIC. The MSI is generated by a Memory Write to address 0FEEx_xxxxh. Three
32-bit registers exist in the PCI Express controller to support this mechanism. The default values of
Bit Field
Default &
Access
Description
7:0 00h Reserved
Bit Field
Default &
Access
Description
7:0 05h
RO
CAP_ID. Capability Identification
05h = Message Signaled Interrupts capability list
Bit Field
Default &
Access
Description
7:0 64h
RO
Next Capability Pointer. This field points to the next Capability ID in this device.