Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 143
Register Descriptions
3.8.33 PMCSR – Power Management Status and Control (D2:F0)
Address Offset: 54 – 55h
Access: RO, R/W
Size: 16 Bits
Default: 0000h
This register identifies the capabilities for PM.
3.8.34 PMCSRBSE – Power Management Status and Control
Bridge Extensions (D2:F0)
Address Offset: 56h
Access: RO
Size: 8 Bits
Default: 00h
This register identifies the capabilities for PM.
Bit Field
Default &
Access
Description
15 0b
RO
PME Status. Indicates/clears PME# assertion. Only for generated PME, not
forwarded PME. Field not supported by MCH. This bit is sticky.
14:13 00b
RO
Data Scale. Not Applicable.
12:9 0h
RO
Data Select. Not Applicable.
8 0b
R/W
PME Enable. Controls PME# assertion. This bit is sticky through reset. Writes to
this field have no effect. This bit is sticky.
0 = This device will not assert PME#
1 = Enables this device to assert PME#
7:2 00h
RO
Reserved
1:0 00b
RO
Power State. Since the PCI Express bridge device supports only the D0 state,
writes to this field have no effect.
Bit Field
Default &
Access
Description
7 0b
RO
Bus Power/Clock Control Enable. Not applicable.
6 0b
RO
B2/B3 Support. Not applicable.
5:0 00h Reserved