Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 141
Register Descriptions
3.8.29 VS_STS1 – Vendor Specific Status Register 1 (D2:F0)
Address Offset: 47h
Access: RO, R/WC
Size: 8 Bits
Default: 00h
This register is for vendor specific status
3.8.30 PMCAPID – Power Management Capabilities Structure
(D2:F0)
Address Offset: 50h
Access: RO
Size: 8 Bits
Default: 01h
This register identifies the capability structure and points to the next structure.
Bit Field
Default &
Access
Description
7:0 00h Reserved
Bit Field
Default &
Access
Description
7:2 0b Reserved
1 0b
RO
Link Active. Bit will report whether transactions are being sent or aborted by the
downstream transaction control, which is determined by the “link_active” status
from the link layer reflected in this status bit.
1 = link up.
0 = link down.
0 0b
R/WC
PMETOA. PME Turn Off Acknowledge
0 = Software writes a ‘1’ to clear this bit. The bit is also cleared when the link
layer is in the DL_down state.
1 = PMETOR is ON and the acknowledge is returned from the link. The Turn Off
request bit is cleared.
Bit Field
Default &
Access
Description
7:0 01h
RO
CAP_ID. Capability ID
01h = Vendor dependent capability pointers