138 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
The CAPPTR provides the offset that is the pointer to the location where the first set of capabilities
registers is located.
3.8.23 INTRLINE – Interrupt Line Register (D2:F0)
Address Offset: 3Ch
Access: R/W
Size: 8 Bits
Default: 00h
3.8.24 INTRPIN – Interrupt Pin Register (D2:F0)
Address Offset: 3Dh
Access: R/WO
Size: 8 Bits
Default: 02h
Bit Field
Default &
Access
Description
7:0 50h
RO
Capabilities Pointer (CAP_PTR). Pointer to first PCI Express Capabilities
Structure register block, which is the first of the chain of capabilities.
Bit Field
Default &
Access
Description
7:0 00h
R/W
Interrupt Connection. BIOS writes the interrupt routing information to this
register to indicate which input of the interrupt controller this device is connected
to.
Bit Field
Default &
Access
Description
7:0 01h
R/WO
Interrupt Pin. Designates the interrupt pin mapping for this device.
00h = Reserved
01h = INTA#
02h = INTB#
03h = INTC#
04h = INTD#
05 – FFh = Reserved