Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 137
Register Descriptions
3.8.20 PMBASU – Prefetchable Memory Base Upper Address
Register (D2:F0)
Address Offset: 28h
Access: RO, R/W
Size: 8 Bits
Default: 0Fh
These register expands the prefetchable memory base address by four bits. All other bits are
reserved.
3.8.21 PMLMTU – Prefetchable Memory Limit Upper Address
Register (D2:F0)
Address Offset: 2Ch
Access: RO, R/W
Size: 8 Bits
Default: 00h
3.8.22 CAPPTR – Capabilities Pointer (D2:F0)
Address Offset: 34h
Access: RO
Size: 8 Bits
Default: 50h
Bit Field
Default &
Access
Description
15:4 000h
R/W
Prefetchable Memory Address Limit (PMLIMIT). Corresponds to A[31:20] of
the upper limit of the address range passed by bridge device across PCI Express.
3:1 000b
RO
Memory addressing mode.
0 1b
RO
Memory Limit Upper Address Enabled.
0 = Memory Limit Upper Address Disabled
1 = Enabled. The limit address is further defined by the upper address bits of the
memory limit upper address register.
Bit Field
Default &
Access
Description
7:4 0h Reserved
3:0 Fh
R/W
Base Upper Address bits. These four bits expand the prefetchable address
base to 36 bits. Corresponds to A[35:32] of the lower limit of the address range
passed by bridge device across PCI Express interface.
Bit Field
Default &
Access
Description
7:4 0h Reserved
3:0 0h
R/W
Limit Upper Address bits. These four bits expand the prefetchable address limit
to 36 bits. Corresponds to A[35:32] of the upper limit of the address range passed
by bridge device across PCI Express interface.