136 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.8.18 PMBASE – Prefetchable Memory Base Address Register
(D2:F0)
Address Offset: 24 – 25h
Access: RO, R/W
Size: 16 Bits
Default: FFF1h
The PMBASE and PMLIMIT registers control the processor-to-PCI Express prefetchable memory
accesses. The upper 12 bits of both registers are read/write and correspond to the upper 12 address
bits A[31:20] of the 32-bit address. For the purpose of address decode, address bits A[19:0] of the
Prefetchable Memory Base Address are assumed to be 0. Similarly, the bridge assumes that the
lower 20 bits of the Prefetchable Memory Limit Address (A[19:0]) are F_FFFFh. Thus, the bottom
of the defined memory address range will be aligned to a 1-Mbyte boundary, and the top of the
defined memory range will be at the top of a 1-MB memory block.
3.8.19 PMLIMIT – Prefetchable Memory Limit Address Register
(D2:F0)
Address Offset: 26 – 27h
Access: RO, R/W
Size: 16 Bits
Default: 0001h
This register controls the processor to PCI Express prefetchable memory accesses. The upper 12
bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32 bit
address. For the purpose of address decode, bits A[19:0] are assumed to be F_FFFFh. Thus, the top
of the defined memory address range will be at the top of a 1MB aligned memory block.
Bit Field
Default &
Access
Description
15:4 000h
R/W
Memory Address Limit (MLIMIT). Corresponds to A[31:20] of the memory
address that corresponds to the upper limit of the range of memory accesses that
will be passed by the device bridge to PCI Express.
3:0 0h Reserved
Bit Field
Default &
Access
Description
15:4 FFFh
R/W
Prefetchable Memory Address Base (PMBASE). Corresponds to A[31:20] of
the lower limit of the address range passed by bridge device across PCI Express.
3:1 000b
RO
Memory addressing mode.
0 1b
RO
Memory Base Upper Address Enabled.
0 = Memory Base Upper Address Disabled
1 = Enable. The base address is further defined by the upper address bits of the
memory base upper address register.