Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 135
Register Descriptions
3.8.16 MBASE – Memory Base Address Register (D2:F0)
Address Offset: 20 – 21h
Access: R/W
Size: 16 Bits
Default: FFF0h
The MBASE and MLIMIT registers control the processor to PCI Express non-prefetchable
memory access routing based on the following formula:
MBASE Address MLIMIT
The upper 12 bits of both registers are read/write and correspond to the upper 12 address bits
A[31:20] of the 32-bit address. The bottom four bits of these registers are read-only and return
zeroes when read. These registers must be initialized by configuration software. For the purpose of
address decode address bits A[19:0] of the Memory Base Address are assumed to be 0. Similarly,
the bridge assumes that the lower 20 bits of the Memory Limit Address (A[19:0]) are F_FFFFh.
Thus, the bottom of the defined memory address range will be aligned to a 1-Mbyte boundary, and
the top of the defined memory range will be at the top of a 1-MB memory block.
Note: Memory range covered by MBASE and MLIMIT registers are used to map non-prefetchable PCI
Express address ranges (typically where control/status memory-mapped I/O data structures of the
graphics controller will reside) and PMBASE and PMLIMIT are used to map prefetchable address
ranges (typically graphics local memory). This segregation allows for the application of the write
combine space attribute to be performed in a true plug-and-play manner to the prefetchable address
range for improved PCI Express memory access performance.
Note also that configuration software is responsible for programming all address range registers
(prefetchable, non-prefetchable) with the values that provide exclusive address ranges (i.e. prevent
overlap with each other and/or with the ranges covered with the main memory). There is no
provision in the MCH hardware to enforce prevention of overlap and operations of the system in
the case of overlap are not guaranteed.
3.8.17 MLIMIT – Memory Limit Address Register (D2:F0)
Address Offset: 22 – 23h
Access: R/W
Size: 16 Bits
Default: 0000h
5 0b
RO
66 MHz Capable. Not Applicable.
4:0 00h Reserved
Bit Field
Default &
Access
Description
Bit Field
Default &
Access
Description
15:4 FFFh
R/W
Memory Address Base (MBASE). Corresponds to A[31:20] of the lower limit of
the memory range that will be passed by the device bridge to PCI Express.
3:0 0h Reserved
