Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 133
Register Descriptions
3.8.13 IOBASE – I/O Base Address Register (D2:F0)
Address Offset: 1Ch
Access: RO, R/W
Size: 8 Bits
Default: F0h
The IOBASE and IOLIMIT registers control the processor-to-PCI Express I/O access routing
based on the following formula:
IOBASE Address IOLIMIT
Only the upper four bits are programmable. For the purpose of address decode address bits A[11:0]
are treated as 0. Thus the bottom of the defined I/O address range will be aligned to a 4-KB
boundary.
3.8.14 IOLIMIT – I/O Limit Address Register (D2:F0)
Address Offset: 1Dh
Access: R/W
Size: 8 Bits
Default: 00h
This register controls the processor to PCI Express I/O access routing based on the following
formula:
IOBASE Address IOLIMIT
Only the upper four bits are programmable. For the purpose of address decode address bits A[11:0]
are assumed to be FFFh. Thus, the top of the defined I/O address range will be at the top of a 4KB
aligned address block.
Bit Field
Default &
Access
Description
7:4 Fh
R/W
I/O Address Base (IOBASE). Corresponds to A[15:12] of the I/O addresses
passed by the device bridge to PCI Express
3:0 0h
RO
I/O Addressing Capability. Only 16-bit I/O addressing is supported, so these
bits are hardwired to ‘0’.
Bit Field
Default &
Access
Description
7:4 0h
R/W
I/O Address Limit (IOLIMIT). Corresponds to A[15:12] of the I/O address limit of
device. Devices between this upper limit and IOBASE will be passed to PCI
Express.
3:0 0h
RO
I/O Addressing Capability. Only 16-bit I/O addressing is supported, so these bits
are hardwired to ‘0’.