132 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.8.10 PBUSN – Primary Bus Number (D2:F0)
Address Offset: 18h
Access: RO
Size: 8 Bits
Default: 00h
This register identifies that “virtual” PCI-to-PCI bridge is connected to bus 0.
3.8.11 SBUSN – Secondary Bus Number (D2:F0)
Address Offset: 19h
Access: R/W
Size: 8 Bits
Default: 00h
This register identifies the bus number assigned to the second bus side of the “virtual” PCI-to-PCI
bridge (the PCI Express connection). This number is programmed by the PCI configuration
software to allow mapping of configuration cycles to a subordinate device connected to PCI
Express.
3.8.12 SUBUSN – Subordinate Bus Number (D2:F0)
Address Offset: 1Ah
Access: R/W
Size: 8 Bits
Default: 00h
This register is programmed by PCI configuration software to the highest numbered subordinate
bus (if any) that resides below another bridge device below the secondary PCI Express interface.
Bit Field
Default &
Access
Description
7:0 00h
RO
Primary Bus Number (BUSN). Configuration software typically programs this
field with the number of the bus on the primary side of the bridge. Since device is
an internal device and its primary bus is always 0, these bits are hardwired to ‘0’.
Bit Field
Default &
Access
Description
7:0 00h
R/W
Secondary Bus Number (BUSN). This field is programmed by configuration
software with the bus number of the PCI Express port.
Bit Field
Default &
Access
Description
7:0 00h
R/W
Subordinate Bus Number (BUSN). This register is programmed by
configuration software with the number of the highest subordinate bus that lies
behind the device bridge.
