130 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.8.5 RID – Revision Identification (D2:F0)
Address Offset: 08h
Access: RO
Size: 8 Bits
Default: 09h
This register contains the revision number of the device.
3.8.6 SUBC – Sub-Class Code (D2:F0)
Address Offset: 0Ah
Access: RO
Size: 8 Bits
Default: 04h
This register contains the Sub-Class Code for the device.
4 1b
RO
Capabilities List. An Extended Capability List item exists
3 0b
RO
INTx Status. This bit does not get set for interrupts forwarded up from
downstream devices, or for messages converted to interrupts by the root port.
The INTx Assertion Disable bit has no effect on the setting of this bit. This bit is
not set for an MSI.
0 = An interrupt is NOT pending internal to this device
1 = An interrupt is pending internal to this device
2:0 00h Reserved
Bit Field
Default &
Access
Description
Bit Field
Default &
Access
Description
7:0 00h
RO
Revision Identification Number (RID). This value indicates the revision
identification number for the device. It is always the same as the value in Device
0 RID.
09h = C1 stepping.
0Ah = C2 stepping.
0Ch = C4 stepping.
Bit Field
Default &
Access
Description
7:0 04h
RO
Sub-Class Code (SUBC). This value indicates the category of Bridge into which
device falls.
04h = PCI to PCI Bridge.