Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 129
Register Descriptions
3.8.4 PCISTS – PCI Status Register (D2:F0)
Address Offset: 06 – 07h
Access: RO, R/WC
Size: 16 Bits
Default: 0010h
PCISTS2 is a 16-bit status register that reports the occurrence of error conditions associated with
the primary side of the “virtual” PCI-to-PCI bridge embedded within the MCH.
Bit Field
Default &
Access
Description
15 0b
RO
Detected Parity Error (DPE). Parity is supported on the primary side of this
device. Since the parity is not checked on the downstream side from the core, this
bit can never be set.
0 = No Poisoned TLP detected
1 = Poisoned TLP detected
14 0b
R/WC
Signaled System Error (SSE). Indicates whether or not a Hub Interface SERR
message was generated by this device. For the root port the fatal and non-fatal
messages can be either received or virtual messages that are forwarded for
reporting.
0 = SERR message not generated by this device. Software clears this bit by
writing a ‘1’ to the bit location.
1 = This device was the source of fatal or non-fatal error that has been enabled
for generation of a System Error.
13 0b
R/WC
Received Master Abort Status (RMAS). Indicates whether or not this PCI
Express device received a completion with Unsupported Request Completion
status.
0 = No Master Abort received. Software clears this bit by writing a ‘1’ to the bit
location.
1 = Set when this PCI Express device receives a completion with Unsupported
Request Completion Status.
12 0b
R/WC
Received Target Abort Status (RTAS). Indicates whether or not this PCI
Express device received a completion with Completer Abort Completion Status.
0 = No Target Abort received. Software clears this bit by writing a ‘1’ to the bit
location.
1 = Set when this PCI Express device receives a completion with Completer
Abort Completion Status
11 0b
RO
Signaled Target Abort Status (STAS). Indicates whether or not this PCI Express
device completed a request using Completer Abort Completion Status. Not
applicable to the primary side.
10:9 00b
RO
DEVSEL# Timing (DEVT). Not Applicable.
8 0b
R/WC
Master Data Parity Error Detected (DPD). Parity is supported on the primary
side of this device.
0 = No Master Parity Error detected. Software clears this bit by writing a ‘1’ to the
bit location.
1 = Set when this PCI Express device receives a completion marked poisoned,
or when this device poisons a write Request. This bit can only be set if the
Parity Error Enable bit is set.
7 0b
RO
Fast Back-to-Back (FB2B). Not Applicable.
6 0b Reserved
5 0b
RO
66 MHz Capable. Not Applicable.
