128 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.8.3 PCICMD – PCI Command Register (D2:F0)
Address Offset: 04 – 05h
Access: RO, R/W
Size: 16 Bits
Default: 0000h
Many of these bits are not applicable since the primary side of this device is not an actual PCI bus.
Bit Field
Default &
Access
Description
15:11 00h Reserved
10 0b
R/W
INTx Disable. Controls the ability of the PCI Express device to assert INTx
interrupts. This bit only applies to legacy interrupts, and not MSIs. Also, this bit
has no effect on PCI Express messages that are converted to legacy interrupts,
only internal, device generated interrupts.
0 = Enable INTx assertion
1 = Disable INTx assertion (devices are prevented from asserting INTx)
9 0b
RO
Fast Back-to-Back Enable (FB2B). Not Applicable.
8 0b
R/W
SERR Enable (SERRE). This bit is a global enable bit for Device error
messaging.
0 = No SERR, SCI, or SMI message is generated by the MCH for device (unless
enabled through enhanced configuration registers).
1 = Enable SERR, SCI, or SMI messages over HI or asserting MCERR# for
specific device error conditions.
7 0b
RO
Address/Data Stepping (ADSTEP). Not applicable.
6 0b
R/W
Parity Error Enable (PERRE). See the PCI Express Interface Specification, Rev
1.0a, for details.
0 = Parity Errors are logged in the status register, but no other action is taken.
1 = Normal action is taken upon detection of Parity Error, as well as logging.
5 0b
RO
VGA Palette Snoop. Not Applicable.
4 0b
RO
Memory Write and Invalidate. Not applicable.
3 0b
RO
Special Cycle Enable. Not applicable.
2 0b
R/W
Bus Master Enable (BME). This bit controls the PCI Express port’s ability to
issue memory and I/O read/write requests on behalf of subordinate devices. Note
that MSI interrupt messages are in-band memory writes.
0 = Disable MSI interrupt messages. The port will not respond to any I/O or
memory transaction originating on the secondary interface.
1 = Enable.
1 0b
R/W
Memory Access Enable (MAE). Controls access to the Memory and
Prefetchable memory address ranges defined in the MBASE2, MLIMIT2,
PMBASE2, and PMLIMIT2 registers.
0 = Disable all of device memory space.
1 = Enable
0 0b
R/W
I/O Access Enable (IOAE). Controls access to the I/O address range defined in
the IOBASE2 and IOLIMIT2 registers.
0 = Disable device I/O space.
1 = Enable
