124 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.7.12 CAPPTR- Capabilities Pointer (D1:F0)
Address Offset: 34h
Access: RO
Size: 8 Bits
Default: B0h
The CAPPTR provides the offset that is the pointer to the location where the first set of capabilities
registers is located.
3.7.13 INTRLINE- Interrupt Line Register (D1:F0)
Address Offset: 3Ch
Access: R/W
Size: 8 Bits
Default: 00h
3.7.14 INTRPIN- Interrupt Pin Register (D1:F0)
Address Offset: 3Dh
Access: RO
Size: 8 Bits
Default: 01h
3.8 PCI Express Port A Registers (D2:F0)
Device 2 is the PCI Express port A (in x8 mode) or port A0 (in x4 mode) virtual PCI-to-PCI bridge.
The registers described here include both the standard configuration space as well as the enhanced
configuration space (starting at offset 100h).
Bit Field
Default &
Access
Description
7:0 B0h
RO
Pointer to MSI Capabilities Structure.
Bit Field
Default &
Access
Description
7:0 00h
R/W
Interrupt Connection. BIOS writes the interrupt routing information
to this register to indicate which input of the interrupt controller this
device is connected to.
Bit Field
Default &
Access
Description
7:0 01h
RO
Interrupt Pin. DMA always uses INTA# as its interrupt pin.