Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 121
Register Descriptions
3.7.4 PCISTS-PCI Status Register (D1:F0)
Address Offset: 06 – 07h
Access: RO, R/WC
Size: 16 Bits
Default: 0010h
3.7.5 RID- Revision Identification (D1:F0)
Address Offset: 08h
Access: RO
Size: 8 Bits
Default: 09h
8 0b
R/W
SERR Enable (SERRE). A global enable bit for Device 1 SERR
messaging. The MCH does not have an SERR# signal. The MCH
communicates the SERR condition by sending an SERR message over
HL_A to the ICH.
0 = The SERR message is not generated by the MCH for Device 1,
Function 0.
1 = The MCH is enabled to generate SERR messages over HL_A for
specific Device 1 error conditions that are individually enabled in the
ERRCMD register. The error status is reported in the ERRSTAT and
PCISTS registers.
7:2 00h Reserved
1 0b
R/W
Memory Access Enable (MAE).
0 = Device 1’s memory space is disabled.
1 = Enables the DMA Low Base Address register functionality. This bit
would also have enabled the MBASE, MLINIT, PMBASE, and
PMLINIT registers, but these are not implemented for DMA.
0 0b Reserved
Bit Field
Default &
Access
Description
Bit Field
Default &
Access
Description
15 0b Reserved
14 0b
R/WC
Signaled System Error (SSE).
0 = Software sets SSE to 0 by writing a 1 to this bit.
1 = Device 1 generated an SERR message over HL_A for any enabled
Device 1 error condition. Device 1 error conditions are enabled in the
PCICMD and ERRCMD registers. Device 1 error flags are read/reset
from the PCISTS or ERRSTAT registers.
13:5 000h Reserved
4 1b
RO
Indicates support for the capability list.
3 0b
RO
In Tx Status. The interrupt assertion disable bit has no effect on the setting
of this bit. This bit is not set for an MSI.
0 = An INTx interrupt is NOT pending
1 = An INTx interrupt is pending internal to the device.
2:0 0h Reserved