12 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
5-20 DWORD Memory Read Protocol (SMBus Word Write / Word Read,
PEC Disabled)................................................................................................................. 257
5-21 WORD Configuration Wrote Protocol (SMBus Byte Write, PEC Disabled)..................... 258
7-1 MCH Ballout Diagram (Top View) ................................................................................... 267
7-2 MCH Package Dimensions (Bottom View)...................................................................... 278
7-3 MCH Package Dimensions (Side View).......................................................................... 278
7-4 MCH Package Dimensions (Top View)........................................................................... 279
Tables
2-1 System Bus Signal Description......................................................................................... 23
2-2 DDR Channel_A Interface Signals.................................................................................... 26
2-3 DDR Channel_B Interface Signals.................................................................................... 27
2-4 DDR Interface Shared Signals .......................................................................................... 27
2-5 PCI Express Naming Convention Definitions.................................................................... 28
2-6 Example Naming Convention Conversions....................................................................... 28
2-7 PCI Express* Interface Port A Signals .............................................................................. 28
2-8 PCI Express Interface Port B Signals ............................................................................... 29
2-9 PCI Express Interface Port C Signals ............................................................................... 29
2-10 PCI Express Interface Shared Signals.............................................................................. 30
2-11 Hub Interface Signals........................................................................................................ 30
2-12 Reset, Power, and Miscellaneous Signals ........................................................................ 30
3-1 PCI Device Number Assignment....................................................................................... 34
3-2 MCH Control PCI Configuration Register Map (D0:F0)..................................................... 41
3-3 PAM Associated Attribute Bits .......................................................................................... 51
3-4 DIMM to DRA Register Mapping....................................................................................... 53
3-5 Error Reporting PCI Configuration Register Map (D0:F1)................................................. 73
3-6 DMA Controller PCI Configuration Register Map (D1:F0)............................................... 119
3-7 PCI Express Port A PCI Configuration Register Map (D2:F0) ........................................ 125
3-8 PCI Express Port A1 PCI Configuration Register Map (D3:F0) ...................................... 178
3-9 PCI Express Port B PCI Configuration Register Map (D4:F0) ........................................ 181
3-10 PCI Express Port B1 PCI Configuration Register Map (D5:F0) ...................................... 184
3-11 PCI Express Port C PCI Configuration Register Map (D6:F0) ........................................ 187
3-12 PCI Express Port C1 PCI Configuration Register Map (D7:F0) ...................................... 189
3-13 Extended Configuration Registers PCI Configuration Register Map (D8:F0).................. 192
4-1 Supported SMM Ranges................................................................................................. 210
5-1 DBI Signals to Data Bit Mapping..................................................................................... 215
5-2 FSB Parity Matrix ............................................................................................................ 215
5-3 Supported DDR Technologies ........................................................................................ 216
5-4 Memory Interface Capacities .......................................................................................... 216
5-5 Dual Channel Non-Symmetric Address Map .................................................................. 223
5-6 Single Channel Non-Symmetric Address Map................................................................ 225
5-7 Dual Channel Symmetric Address Map .......................................................................... 226
5-8 DDR Channel A Clock to DIMM assignment................................................................... 228
5-9 DDR Channel B Clock to DIMM assignment................................................................... 228
5-10 MCH Clocking Interfaces ................................................................................................ 232
5-11 MCH Reset Classes........................................................................................................ 234
5-12 Reset Sequences and Durations .................................................................................... 237
5-13 Comparison of Error Classification.................................................................................. 245
5-14 SMBus Transaction Field Summary................................................................................ 252
6-1 Absolute Maximum Ratings ............................................................................................ 259
6-2 Operating Condition Power Supply Rails........................................................................ 259
6-3 Signal Groups FSB Interface .......................................................................................... 260
6-4 Signal Groups Memory (DDR and DDR2) Interface........................................................ 260
6-5 Signal Groups PCI Express Interface ............................................................................. 261
6-6 Signal Groups Hub Interface........................................................................................... 261
6-7 Signal Groups Reset and Miscellaneous ........................................................................ 261