Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 119
Register Descriptions
3.6.72 DRAM_ERR_CTL – DRAM Error Control Register (D0:F1)
Address Offset: EC – EFh
Access: R/W
Size: 32 Bits
Default: 0000_0000h
This register controls the MCH handling of errors on incoming data streams into the MCH core
from the DRAM interface.
3.7 DMA Controller Registers (D1:F0)
For additional register details, please see your Intel Field Representative.
Bit Field
Default &
Access
Description
31:19 0000h Reserved
18 0b
R/W
Data Poisoning Enable. This bit controls whether or not the MCH marks data as
“poisoned” when a parity error is detected on incoming data from the DRAM I/F.
0 = Errors will not be propagated, only good internal parity generated.
1 = Error Poisoning Enabled. Incoming data with parity errors will be marked as
“poisoned” before being sent on towards its destination when in either 72-bit
or x4 SDDC ECC mode via the DRC register.
17:0 0 Reserved
Table 3-6. DMA Controller PCI Configuration Register Map (D1:F0)
Address
Offset
Mnemonic Register Name Access Default
00 – 01h VID Vendor Identification RO 8086
02 – 03h DID Device Identification RO 3594h
04 – 05h PCICMD PCI Command Register R/W 0000h
06 – 07h PCISTS PCI Status Register RO, R/WC 0010h
08h RID Revision Identification RO 09h
0Ah SUBC Sub-Class Code RO 80h
0Bh BCC Base Class Code RO 08h
0Eh HDR Header Type RO 00h
10 – 13h DMALBAR DMA Low Base Address Register R/W,RO 0000_0000h
2C – 2Dh SVID Subsystem Vendor Identification R/WO 0000h
2E – 2Fh SID Subsystem Identification R/WO 0000h
34h CAPPTR Capabilities Pointer RO B0h
3Ch INTRLINE Interrupt Line Register R/W 00h
3Dh INTRPIN Interrupt Pin Register RO 00h