116 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.6.67 DRAM_DED_D3B – DRAM DIMM3 Channel B DED Counter
Register (D0:F1)
Address Offset: DA – DBh
Access: R/W
Size: 16 Bits
Default: 0000h
Counter for DED errors occurring for logical DIMM3 of channel B. The functionality of this
counter is described in Section 3.6.50 on page 3-109. The bits in this register are sticky through
reset.
3.6.68 DIMM_THR_EX – DIMM Threshold Exceeded Register
(D0:F1)
Address Offset: DC – DDh
Access: R/WC
Size: 16 Bits
Default: 0000h
Preserves knowledge of DIMM error thresholds exceeded. The bits in this register are sticky
through reset.
Bit Field
Default &
Access
Description
15:0 0000h
RO
DIMM3 Channel B DED Count.
Bit Field
Default &
Access
Description
15 0b
R/WC
Channel B logical DIMM 3 DED Threshold Status. This bit is sticky through
reset. Software can clear this bit by writing a ‘1’ to the bit location.
0 = Threshold not exceeded
1 = Threshold exceeded.
14 0b
R/WC
Channel B logical DIMM 2 DED Threshold Status. This bit is sticky through
reset. Software can clear this bit by writing a ‘1’ to the bit location.
0 = Threshold not exceeded
1 = Threshold exceeded
13 0b
R/WC
Channel B logical DIMM 1 DED Threshold Status. This bit is sticky through
reset. Software can clear this bit by writing a ‘1’ to the bit location.
0 = Threshold not exceeded
1 = Threshold exceeded
12 0b
R/WC
Channel B logical DIMM 0 DED Threshold Status. This bit is sticky through
reset. Software can clear this bit by writing a ‘1’ to the bit location.
0 = Threshold not exceeded
1 = Threshold exceeded
11 0b
R/WC
Channel B logical DIMM 3 SEC Threshold Status. This bit is sticky through
reset. Software can clear this bit by writing a ‘1’ to the bit location.
0 = Threshold not exceeded
1 = Threshold exceeded