Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 115
Register Descriptions
3.6.64 DRAM_SEC_D2B – DRAM DIMM2 Channel B SEC Counter
Register (D0:F1)
Address Offset: D4 – D5h
Access: R/W
Size: 16 Bits
Default: 0000h
Counter for SEC errors occurring for logical DIMM2 of channel B. The functionality of this
counter is described in Section 3.6.50 on page 3-109. The bits in this register are sticky through
reset.
3.6.65 DRAM_DED_D2B – DRAM DIMM2 Channel B DED Counter
Register (D0:F1)
Address Offset: D6 – D7h
Access: R/W
Size: 16 Bits
Default: 0000h
Counter for DED errors occurring for logical DIMM2 of channel B. The functionality of this
counter is described in Section 3.6.50 on page 3-109. The bits in this register are sticky through
reset.
3.6.66 DRAM_SEC_D3B – DRAM DIMM3 Channel B SEC Counter
Register (D0:F1)
Address Offset: D8 – D9h
Access: R/W
Size: 16 Bits
Default: 0000h
Counter for SEC errors occurring for logical DIMM3 of channel B. The functionality of this
counter is described in Section 3.6.50 on page 3-109. The bits in this register are sticky through
reset.
Bit Field
Default &
Access
Description
15:0 0000h
R/W
DIMM2 Channel B SEC Count.
Bit Field
Default &
Access
Description
15:0 0000h
R/W
DIMM2 Channel B DED Count.
Bit Field
Default &
Access
Description
15:0 0000h
R/W
DIMM3 Channel B SEC Count.