114 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.6.61 DRAM_DED_D0B – DRAM DIMM0 Channel B DED Counter
Register (D0:F1)
Address Offset: CE – CFh
Access: R/W
Size: 16 Bits
Default: 0000h
Counter for DED errors occurring for logical DIMM0 of channel B. The functionality of this
counter is described in Section 3.6.50 on page 3-109. The bits in this register are sticky through
reset.
3.6.62 DRAM_SEC_D1B – DRAM DIMM1 Channel B SEC Counter
Register (D0:F1)
Address Offset: D0 – D1h
Access: R/W
Size: 16 Bits
Default: 0000h
Counter for SEC errors occurring for logical DIMM1 of channel B. The functionality of this
counter is described in Section 3.6.50 on page 3-109. The bits in this register are sticky through
reset.
3.6.63 DRAM_DED_D1B – DRAM DIMM1 Channel B DED Counter
Register (D0:F1)
Address Offset: D2 – D3h
Access: R/W
Size: 16 Bits
Default: 0000h
Counter for DED errors occurring for logical DIMM1 of channel B. The functionality of this
counter is described in Section 3.6.50 on page 3-109. The bits in this register are sticky through
reset.
Bit Field
Default &
Access
Description
15:0 0000h
R/W
DIMM0 Channel B DED Count.
Bit Field
Default &
Access
Description
15:0 0000h
R/W
DIMM1 Channel B SEC Count.
Bit Field
Default &
Access
Description
15:0 0000h
R/W
DIMM1 Channel B DED Count.