Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 113
Register Descriptions
3.6.59 DRAM_SEC2_ADD – DRAM Next Single-Bit Error Correct
Address Register (D0:F1)
Address Offset: C8 – CBh
Access: RO
Size: 32 Bits
Default: 0000_0000h
Captures the address of the next SEC error (either normal or scrub read) occurring in the memory
system corresponding to the bit set in the NERR register. The value in this register correspond to a
correctable error being set in the DRAM_NERR register (either bit 0 or 8 depending on channel).
The bits in this register are sticky through reset.
When mirroring mode is enabled, the address reported by this register will reflect an address of the
primary DIMM, and will never reflect an address of the mirrored DIMM, regardless of which
DIMM had the error.
3.6.60 DRAM_SEC_D0B – DRAM DIMM0 Channel B SEC Counter
Register (D0:F1)
Address Offset: CC – CDh
Access: R/W
Size: 16 Bits
Default: 0000h
Counter for SEC errors occurring for logical DIMM0 of channel B. The functionality of this
counter is described in Section 3.6.50 on page 3-109. The bits in this register are sticky through
reset.
Bit Field
Default &
Access
Description
31 0b Reserved
30:2 000_0000h
RO
Next Correctable Error Address. This field contains address bits 35:12 for the
next correctable error. This field is set by HW when the Correctable Read Memory
Error bit in the DRAM_SERR register is set. This value represents a system
address. This field can only be reset by a PWRGD reset.
1:0 00b Reserved
Bit Field
Default &
Access
Description
15:0 0000h
R/W
DIMM0 Channel B SEC Count.