Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 111
Register Descriptions
3.6.53 DRAM_DED_D1A – DRAM DIMM1 Channel A DED Counter
Register (D0:F1)
Address Offset: B6 – B7h
Access R/W
Size: 16 Bits
Default: 0000h
Counter for DED errors occurring for logical DIMM1 of channel A. The functionality of this
counter is described in Section 3.6.50 on page 3-109. The bits in this register are sticky through
reset.
3.6.54 DRAM_SEC_D2A – DRAM DIMM2 Channel A SEC Counter
Register (D0:F1)
Address Offset: B8 – B9h
Access: R/W
Size: 16 Bits
Default: 0000h
Counter for SEC errors occurring for logical DIMM2 of channel A. The functionality of this
counter is described in Section 3.6.50 on page 3-109. The bits in this register are sticky through
reset.
3.6.55 DRAM_DED_D2A – DRAM DIMM2 Channel A DED Counter
Register (D0:F1)
Address Offset: BA – BBh
Access: R/W
Size: 16 Bits
Default: 0000h
Counter for DED errors occurring for logical DIMM2 of channel A. The functionality of this
counter is described in Section 3.6.50 on page 3-109. The bits in this register are sticky through
reset.
Bit Field
Default &
Access
Description
15:0 0000h
R/W
DIMM1 Channel A DED Count.
Bit Field
Default &
Access
Description
15:0 0000h
R/W
DIMM2 Channel A SEC Count.
Bit Field
Default &
Access
Description
15:0 0000h
R/W
DIMM2 Channel A DED Count.