108 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.6.47 DRAM_DED_ADD – DRAM DED Error Address (D0:F1)
Address Offset: A4 – A7h
Access RO
Size 32 Bits
Default 0000_0000h
Captures the address of the first DED error (uncorrectable, non-scrub engine) occurring in the
memory system. If DED Retry is enabled, this register will capture the address of the first failed
retry. The value in this register is only valid if the Uncorrectable Read Memory Error bit in either
the DRAM_FERR or DRAM_NERR register has been set. The bits in this register are sticky
through reset.
When mirroring mode is enabled, the address reported by this register will reflect an address of the
primary DIMM, and will never reflect an address of the mirrored DIMM, regardless of which
DIMM had the error.
3.6.48 DRAM_SCRB_ADD – DRAM Scrub Error Address Register
(D0:F1)
Address Offset: A8 – ABh
Access RO
Size 32 Bits
Default 0000_0000h
Captures the address of the first uncorrectable error encountered by either the periodic memory
scrubber or the sparing engine. The contents of this register correspond to the errors bits 2 and 10
of the DRAM_FERR/NERR registers (depending on channel). The bits in this register are sticky
through reset.
When mirroring mode is enabled, the address reported by this register will reflect an address of the
primary DIMM, and will never reflect an address of the mirrored DIMM, regardless of which
DIMM had the error.
Bit Field
Default &
Access
Description
31 0b Reserved
30:2 000_0000h
RO
First Uncorrectable Error Address. This field contains address bits 34:6 for the
first uncorrectable error. If DED Retry is enabled, the address of the first failed
retry will be captured. This field is set by HW, and represents a system address.
This field can only be reset by a PWRGD reset.
1:0 00b Reserved
Bit Field
Default &
Access
Description
31 0b Reserved
30:2 000_0000h
RO
Scrub Error Address. This field contains address bits 34:6 for the first
uncorrectable error encountered by the periodic memory scrubber or the sparing
engine. This field is set by HW, and represents a system address. This field can
only be reset by a PWRGD reset.
1:0 00b Reserved
