106 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.6.42 THRESH_SEC0 – DIMM0 SEC Threshold Register (D0:F1)
Address Offset: 98 – 99h
Access: R/W
Size: 16 Bits
Default: 0000h
Threshold compare value for SEC errors. An Error Threshold Detect is signaled if the logical
DIMM0 SEC counter (Section 3.6.50 on page 3-109) exceeds the value programmed into this
register. The bits in this register are sticky through reset.
3.6.43 THRESH_SEC1 – DIMM1 SEC Threshold Register (D0:F1)
Address Offset: 9A – 9Bh
Access: R/W
Size: 16 Bits
Default: 0000h
Threshold compare value for SEC errors. An Error Threshold Detect is signaled if the logical
DIMM1 SEC counter (Section 3.6.52 on page 3-110) exceeds the value programmed into this
register. The bits in this register are sticky through reset.
3.6.44 THRESH_SEC2 – DIMM2 SEC Threshold Register (D0:F1)
Address Offset: 9C – 9Dh
Access: R/W
Size: 16 Bits
Default: 0000h
Threshold compare value for SEC errors. An Error Threshold Detect is signaled if the logical
DIMM2 SEC counter (Section 3.6.54 on page 3-111) exceeds the value programmed into this
register. The bits in this register are sticky through reset.
1 0b
R/W
Uncorrectable Read Memory Error MCERR# Enable. Generate MCERR#
when Bit 9 or 1 of DRAM_FERR or DRAM_NERR is set.
0 = Disable
1 = Enable
0 0b
R/W
Correctable Read Memory Error MCERR# Enable. Generate MCERR# when
Bit 8 or 0 of DRAM_FERR or DRAM_NERR is set.
0 = Disable
1 = Enable
Bit Field
Default &
Access
Description
Bit Field
Default &
Access
Description
15:0 0000h
R/W
Threshold compare value for logical DIMM0 SEC errors.
Bit Field
Default &
Access
Description
15:0 0000h
R/W
Threshold compare value for logical DIMM1 SEC errors.