104 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.6.40 DRAM_SERRCMD – DRAM SERR Command Register
(D0:F1)
Address Offset: 8Ch
Access R/W
Size 8 Bits
Default 00h
This register enables various errors to generate an SERR HI special cycle. When an error flag is set
in the FERR or NERR registers, it can generate an SERR, SMI, or SCI HI special cycle when
enabled in the SERRCMD, SMICMD, or SCICMD registers, respectively. Note that one and only
one message type can be enabled. These bits apply to both channel A and channel B.
1 0b
R/W
Uncorrectable Read Memory Error SMI Enable. Generate SMI when Bit 9 or 1
of DRAM_FERR or DRAM_NERR is set.
0 = Disable
1 = Enable
0 0b
R/W
Correctable Read Memory Error SMI Enable. Generate SMI when Bit 8 or 0 of
DRAM_FERR or DRAM_NERR is set.
0 = Disable
1 = Enable
Bit Field
Default &
Access
Description
Bit Field
Default &
Access
Description
7 0b
R/W
Memory Test Complete SERR Enable. Generate SERR when Bit 15 or 7 of
DRAM_FERR or DRAM_NERR is set.
0 = Disable
1 = Enable
6 0b
R/W
Poisoned Write to DRAM SERR Enable. Generate SERR when Bit 14 or 6 of
DRAM_FERR or DRAM_NERR is set.
0 = Disable
1 = Enable
5 0b
R/W
DED Retry Initiated SERR Enable. Generate SERR when Bit 13 or 5 of
DRAM_FERR or DRAM_NERR is set.
0 = Disable
1 = Enable
4 0b
R/W
Data Copy Complete SERR Enable. Generate SERR when Bit 12 or 4 of
DRAM_FERR or DRAM_NERR is set.
0 = Disable
1 = Enable
3 0b
R/W
Error Threshold Detect SERR Enable. Generate SERR when Bit 11 or 3 of
DRAM_FERR or DRAM_NERR is set.
0 = Disable
1 = Enable
2 0b
R/W
Scrubber Data Error SERR Enable. Generate SERR when Bit 10 or 2 of
DRAM_FERR or DRAM_NERR is set.
0 = Disable
1 = Enable