Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 101
Register Descriptions
3.6.36 DRAM_NERR – DRAM Next Error Register (D0:F1)
Address Offset: 82 – 83h
Access R/WC
Size 16 Bits
Default 0000h
Signal errors occurring in the memory system. See DRAM_FERR for bit definitions
3.6.37 DRAM_ERRMASK – DRAM Error Mask Register (D0:F1)
Address Offset: 84h
Access R/W
Size 8 Bits
Default 00h
This register masks the DRAM Controller errors and events from being recognized, preventing
them from being logged at the unit or global level, and no interrupt/messages are generated. Note
that these bits apply to both channels A and B. These bits are sticky through reset.
1 0b
R/WC
Uncorrectable Read Memory Error Channel A. Applies to non-scrub (normal
demand fetch) reads and also indicated and unsuccessful retry if retry is enabled.
This bit is sticky through reset. System software clears this bit by writing a ‘1’ to
the location.
0 = No Uncorrectable Non-Scrub Demand Read Memory Error Channel A
1 = Uncorrectable Non-Scrub Demand Read Memory Error Channel A.
Non-fatal.
0 0b
R/WC
Correctable Read Memory Error Channel A. SEC (Single Bit Error Correction)
detected by normal demand requests or scrubs are counted, and logged in
FERR/NERR. This bit is sticky through reset. System software clears this bit by
writing a ‘1’ to the location.
0 = No Correctable Read Memory Error Channel A
1 = Correctable Read Memory Error Channel A. Non-fatal.
Bit Field
Default &
Access
Description
Bit Field
Default &
Access
Description
7 0b
R/W
Memory Test Complete Mask. This bit is sticky through reset.
0 = Allow Memory Test Complete logging and signaling.
1 = Mask Memory Test Complete logging and signaling.
6 0b
R/W
Uncorrectable Error Detected on Write to DRAM Mask. This bit is sticky
through reset.
0 = Allow Poisoned Write to DRAM detection and signaling.
1 = Mask Poisoned Write to DRAM detection and signaling.
5 0b
R/W
DED Retry Initiated Mask. This bit is sticky through reset.
0 = Allow DED Retry Initiated detection and signaling.
1 = Mask DED Retry Initiated detection and signaling.
4 0b
R/W
Data Copy Complete Mask. This bit is sticky through reset.
0 = Allow Data Copy Complete logging and signaling.
1 = Mask Data Copy Complete logging and signaling.