100 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
11 0b
R/WC
Correctable Error Threshold Detect Channel B. System software clears this bit
by writing a ‘1’ to the location. This bit is sticky through reset.
0 = No Error Threshold detected for Channel B
1 = Error Threshold detected for Channel B. Non-fatal.
10 0b
R/WC
Uncorrectable Scrubber Data Error Channel B. System software clears this bit
by writing a ‘1’ to the location. This bit is sticky through reset.
0 = No Scrubber Error Detected for Channel B
1 = Scrubber Error Detected for Channel B, either for PMS (periodic memory
scrubbing) or Sparing/Mirroring (which uses the scrubber to perform the data
copy). Non-fatal.
9 0b
R/WC
Uncorrectable Read Memory Error Channel B. Applies to non-scrub (normal
demand fetch) reads and also indicated and unsuccessful retry if retry is enabled.
System software clears this bit by writing a ‘1’ to the location. This bit is sticky
through reset.
0 = No Uncorrectable Non-Scrub Demand Read Memory Error Channel B
1 = Uncorrectable Non-Scrub Demand Read Memory Error Channel B.
Non-fatal.
8 0b
R/WC
Correctable Read Memory Error Channel B. SEC (Single Bit Error Correction)
detected by normal demand requests or scrubs are counted, and logged in
FERR/NERR. This bit is sticky through reset. System software clears this bit by
writing a ‘1’ to the location.
0 = No Correctable Read Memory Error Channel B
1 = Correctable Read Memory Error Channel B. Non-fatal.
7 0b
R/WC
Memory Test Complete for Channel A. Not an error condition. This bit is set by
hardware to signal BIOS that HW testing of the channel is complete. This bit is
sticky through reset.
0 = System software clears this bit by writing a ‘1’ to the location.
1 = Hardware-based test of DRAM channel A is complete.
6 0b
R/WC
Uncorrectable Error on Write to Channel A. This bit will be set on a detected
error regardless of ECC mode, even if ECC is disabled. This bit is sticky through
reset. System software clears this bit by writing a ‘1’ to the location.
0 = No poisoned write to DRAM Channel A detected.
1 = Poisoned write to DRAM Channel A detected. Non-fatal.
5 0b
R/WC
DED Retry Initiated for Channel A. This bit is sticky through reset. System
software clears this bit by writing a ‘1’ to the location. This can be set for a normal
demand data read, or for a scrub that is retried.
0 = No DED Retry Initiated for Channel A
1 = DED Retry Initiated for Channel A. Non-fatal.
4 0b
R/WC
Data Copy Complete for Channel A. This bit does not indicate an error
condition. This bit is set by hardware to signal BIOS that data copy for DIMM
sparing or mirroring is complete. This bit sticky through reset.
0 = System software clears this bit by writing a ‘1’ to the location.
1 = Data Copy Complete for Channel A. Non-fatal.
3 0b
R/WC
Correctable Error Threshold Detect Channel A. This bit is sticky through reset.
System software clears this bit by writing a ‘1’ to the location.
0 = No Error Threshold detected for Channel B
1 = Error Threshold detected for Channel B. Non-fatal.
2 0b
R/WC
Uncorrectable Scrubber Data Error Channel A. This bit is sticky through reset.
System software clears this bit by writing a ‘1’ to the location.
0 = No Scrubber Error Detected for Channel A
1 = Scrubber Error Detected for Channel A, either for PMS (periodic memory
scrubbing), mirroring, or Sparing. Non-fatal.
Bit Field
Default &
Access
Description
