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NOT FOR NEW DESIGN
May 2009 Doc ID 10552 Rev 3
This is information on a product still in production but not recommended for new designs.
PSD813F2V PSD854F2V
Flash in-system programmable (ISP) peripherals
for 8-bit MCUs, 3.3 V
FEATURES SUMMARY
■ FLASH IN-SYSTEM PROGRAMMABLE (ISP)
PERIPHERAL FOR 8-BIT MCUS
■ DUAL BANK FLASH MEMORIES
– UP TO 2 Mbit OF PRIMARY FLASH
MEMORY (8 Uniform Sectors, 32K x8)
– UP TO 256 Kbit SECONDARY FLASH
MEMORY (4 Uniform Sectors)
– Concurrent operation: READ from one
memory while erasing and writing the
other
■ UP TO 256 Kbit of SRAM
■ 27 RECONFIGURABLE I/O PORTS
■ ENHANCED JTAG SERIAL PORT
■ PLD WITH MACROCELLS
– Over 3000 Gates of PLD: CPLD and
DPLD
– CPLD with 16 Output Macrocells (OMCs)
and 24 Input Macrocells (IMCs)
– DPLD - user defined internal chip select
decoding
■ 27 INDIVIDUALLY CONFIGURABLE I/O
PORT PINS
The can be used for the following functions:
– MCU I/Os
– PLD I/Os
– Latched MCU address output
– Special function I/Os.
– 16 of the I/O ports may be configured as
open-drain outputs.
■ IN-SYSTEM PROGRAMMING (ISP) WITH
JTAG
– Built-in JTAG compliant serial port allows
full-chip In-System Programmability
– Efficient manufacturing allow easy
product testing and programming
– Use low cost FlashLINK cable with PC
■ PAGE REGISTER
– Internal page register that can be used to
expand the microcontroller address space
by a factor of 256
■ PROGRAMMABLE POWER MANAGEMENT
Figure 1. Packages
■ HIGH ENDURANCE:
– 100,000 Erase/WRITE Cycles of Flash
Memory
– 1,000 Erase/WRITE Cycles of PLD
– 15 Year Data Retention
■ 3.3V±10% SINGLE SUPPLY VOLTAGE
■ STANDBY CURRENT AS LOW AS 25µA
■ Packages are ECOPACK
®
PQFP52 (M)
PLCC52 (J)
TQFP64 (U)
Obsolete Product(s) - Obsolete Product(s)
