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OR2C15A-4S84I

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型号: OR2C15A-4S84I
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功能描述: Field-Programmable Gate Arrays
PDF文件大小: 3148.18 Kbytes
PDF页数: 共192页
制造商: ETC[List of Unclassifed Manufacturers]
制造商LOGO: ETC[List of Unclassifed Manufacturers] LOGO
制造商网址:
捡单宝OR2C15A-4S84I
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120%
ORCA
®
Series 2
Field-Programmable Gate Arrays
Data Sheet
June 1999
Features
High -performance, co st-effective, low-power
0.35 µm CMOS technology (OR2CxxA), 0.3 µm CMOS
technology (OR2TxxA), and 0.25 µm CMOS technology
(OR2TxxB), (four-input look-up table (LUT) delay less
than 1.0 ns with -8 speed grade)
High density (up to 43,200 usable, logic-only gates; or
99,400 gates includin g RAM )
Up to 480 user I/Os (OR2TxxA and OR2TxxB I/Os are
5 V tolerant to allow interconnection to both 3.3 V and
5 V devices, selectable on a per-pin basis)
Four 16-bit look-up tables and four latches/flip-flops per
PFU, ni bb le -oriente d for impleme nti ng 4 -, 8-, 16 -, and /or
32-bit (or wider) bus structures
Eight 3-state buffers per PFU for on-chip bus structures
Fast, on-chip user SRAM has features to simplify RAM
design and increase RAM speed:
— Asynchronous single port: 64 bits/PFU
— Synchronous single port: 64 bits/PFU
— Synchronous dual port: 32 bits/PFU
Improved ability to combine PFUs to create larger RAM
structures using write-port enable and 3-state buffers
Fast, den se m u lti pliers can be cre ated with the mul tip lie r
mode (4 x 1 multiplier/PFU):
— 8 x 8 multiplier requires only 16 PFUs
— 30% increase in speed
Fli p-flop/latch options t o allow programmable priority of
synchronous set/reset vs. clock enable
Enhanced
cascadable
nibble-w ide data path
capabi lities for adders , su btrac tor s, counte rs , mu ltipli ers ,
and comparators inclu din g internal fast-carry operation
Innovative, abundant, and hierarchical nibble-
oriented routing resources that allow automatic u s e of
internal gates for all device densities without sacrificing
performance
Upward bit stream compatible with the
ORCA
ATT2Cxx/
ATT2T xx series of devices
Pinout-co mpatible with new
ORCA
Series 3 FPGAs
TTL or CMOS input levels programmable per pin for the
OR2CxxA (5 V) devices
Individu ally programmable drive capability:
12 mA sink/6 mA source or 6 mA sink/3 mA source
Built-in boundary scan (
IEEE
*1149.1 JTAG) and
3-state all I/O pins, (TS_ALL) testability functions
Multiple configuration options, including simple, low pin-
count s erial ROMs, and pe ripheral or JTA G mo des for in-
system programming (ISP)
Full PCI bus compliance for all devices
Supported by industry-standard CAE tools for design
entry, synthesis, and simulation with
ORCA
Foundry
Development System support (for back-end implementa-
tion)
New, added features (OR2TxxB) have:
— More I/O per package than the OR2TxxA family
— No dedicated 5 V supply (V
DD
5)
— Faster configuration speed (40 MHz)
— Pin s electab le I/O c lamping di odes pr ov ide 5V o r 3.3V
PCI compli ance and 5V tolerance
— Full PCI bu s comp lianc e in both 5V and 3.3V PCI sys-
tems
*
IEEE
is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Table 1
. ORCA
Series 2 FPGAs
* The first number in the usable gat es column assumes 48 gates per PFU (12 gates per f our-i nput LUT/FF pair) for logic-only designs. The
second number assumes 30% of a design is RAM. PFUs used as RAM are counted at four gates per bit, with each PFU capable of
implementing a 16 x 4 RAM (or 256 gates) per PFU.
Device
Usab le
Gates*
# LUTs Register s
Max User
RAM Bits
User
I/Os
Array Size
OR2C04A/OR2T04A 4,800—11,000 400 400 6,400 160 10 x 10
OR2C06A/OR2T06A 6,900—15,900 576 576 9,216 192 12 x 12
OR2C0 8A/O R2T08A 9,400—21,600 784 724 12,544 224 14 x 14
OR2C10A/OR2T10A 12,300—28,300 1024 1024 16,384 256 16 x 16
OR2C12A/OR2T12A 15,600—35,800 1296 1296 20,736 288 18 x 18
OR2C15A/OR2T15A/OR2T15B 19,200—44,200 1600 1600 25,600 320 20 x 20
OR2C26A/OR2T26A 27,600—63,600 2304 2304 36,864 384 24 x 24
OR2C40A/OR2T40A/OR2T40B 43,200—99,400 3600 3600 57,600 480 30 x 30
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