LTC4365
14
4365f
APPLICATIONS INFORMATION
Transients During OV Fault
The circuit of Figure 14 was used to display transients
during an overvoltage condition. The nominal input supply
is 24V and it has an overvoltage threshold of 30V. The
p a r a s i t i c i n d u c t a n c e i s t h a t o f a 1 f o o t w i r e (r o u g h l y 3 0 0 n H ) .
Figure 15 shows the waveforms during an overvoltage
condition at V
IN
. These transients depend on the parasitic
inductance and resistance of the wire along with the ca-
pacitance at the V
IN
node. D1 is an optional power clamp
(TVS, Tranzorb) recommended for applications where
the DC input voltage can exceed 24V and with large V
IN
parasitic inductance. No clamp was used to capture the
waveforms of Figure 15. In order to maintain reverse supply
protection, D1 must be a bi-directional clamp rated for at
least 225W peak pulse power dissipation.
MOSFET Selection
To protect against a negative voltage at V
IN
, the external
N-channel MOSFETs must be configured in a back-to-
back arrangement. Dual N-channel packages are thus the
best choice. The MOSFET is selected based on its power
handling capability, drain and gate breakdown voltages,
and threshold voltage.
The drain to source breakdown voltage must be higher
than the maximum voltage expected between V
IN
and
V
OUT
. Note that if an application generates high energy
transients during normal operation or during Hot Swap™,
the external MOSFET must be able to withstand this
transient voltage.
Due to the high impedance nature of the charge pump that
drives the GATE pin, the total leakage on the GATE pin must
b e k e p t l o w . T h e g a t e d r i v e c u r v e s o f F i g u r e 2 w e r e m e a s u r e d
with a 1μA load on the GATE pin. Therefore, the leakage
on the GATE pin must be no greater than 1μA in order to
match the curves of Figure 2. Higher leakage currents will
result in lower gate drive. The dual N-channel MOSFETs
shown in Table 1 all have a maximum GATE leakage cur-
rent of 100nA. Additionally, Table 1 lists representative
MOSFETs that would work at different values of V
IN
.
Layout Considerations
The trace length between the V
IN
pin and the drain of the
external MOSFET should be minimized, as well as the
trace length between the GATE pin of the LTC4365 and
the gates of the external MOSFETs.
Place the bypass capacitors at V
OUT
as close as possible
to the external MOSFET. Use high frequency ceramic
capacitors in addition to bulk capacitors to mitigate Hot
Swap ringing. Place the high frequency capacitors closest
to the MOSFET. Note that bulk capacitors mitigate ringing
by virtue of their ESR. Ceramic capacitors have low ESR
and can thus ring near their resonant frequency.
V
IN
UV
OV
SHDN
OV = 30V
4365 F14
V
OUT
FAULT
GATE
M1 M2
V
IN
24V
SI9945
60V
12 INCH WIRE
LENGTH
V
OUT
GND
LTC4365
R2
2370k
R1
40.2k
R3
100k
C
OUT
100μF
+
C
IN
1000μF
D1
OPTIONAL
+
9Ω
2A/DIV
GND
GND
0A
20V/DIV
20V/DIV
4365 F15
250ns/DIV
GATE
V
OUT
V
IN
I
IN
GATE
V
OUT
Figure 14. OV Fault with Large V
IN
Inductance
Figure 15. Transients During OV Fault When No
Tranzorb (TVS) Is Used