30
LTC1417
TYPICAL APPLICATIONS
U
BCLR PORTD,Y %00100000 This sets the SS* output bit to a logic
* low, selecting the LTC1417
TRFLP1 LDAA #$0 Load accumulator A with a null byte for SPI transfer
STAA SPDR This writes the byte into the SPI data register and
* starts the transfer
WAIT1 LDAA SPSR This loop waits for the SPI to complete a serial
* transfer/exchange by reading the SPI Status Register
BPL WAIT1 The SPIF (SPI transfer complete flag) bit is the SPSR’s
* MSB and is set to one at the end of an SPI transfer. The
* branch will occur while SPIF is a zero.
LDAA SPDR Load accumulator A with the current byte of LTC1417 data
* that was just received
STAA 0,X Transfer the LTC1417’s data to memory
INX Increment the pointer
CPX #DIN2+1Has the last byte been transferred/exchanged?
BNE TRFLP1 If the last byte has not been reached, then proceed to
* the next byte for transfer/exchage
BSET PORTD,Y %00100000 This sets the SS* output bit to a logic
* high, de-selecting the LTC1417
LDD DIN1 Load the contents of DIN1 and DIN2 into the double
* accumulator D
LSRD
LSRD Two logical shifts to right justify the 14-bit
* conversion results
STD DIN1 Return right justified data to memory
PULA Restore the A register
PULY Restore the Y register
PULX Restore the X register
RTS
CONVST
BUSY
SCLK
D
OUT
RD
MUX
DATA
CH5
CH3 DATACH2 DATACH1 DATACH0 DATA
CH0 CH1 CH2 CH3
1417 F24
Figure 24. Using the Sample Program In Listing 2, the LTC1417, Combined with the DG408 8-Channel MUX,
Has No Latency Between the Selected Input Voltage and Its Conversion Data as Shown In the Timing Relationship Above
