26
LTC1417
*
*****************************************
* Initiate a LTC1417 conversion *
*****************************************
*
BCLR PORTC,Y %00000001 This sets PORTC, Bit0 output to a logic
* low, initiating a conversion
BSET PORTC,Y %00000001 This resets PORTC, Bit0 output to a logic
* high, returning CONVST to a logic high
*
PULA Restore the A register
PULY Restore the Y register
PULX Restore the X register
RTS
TYPICAL APPLICATIONS
U
Figure 22. This Diagram Shows the Relationship Between the Selected LTC1391 MUX Channel and the Conversion Data Retrieved
from the LTC1417 When Using the Sample Program in Listing A. At Any Point in Time, a Two Conversion Delay Exists Between the
Selected MUX Channel and When Its Data Is Retrieved
CONVST
BUSY
RD
MUX
DATA
ADC
DATA
MUX
OUT
CH5CH4CH3CH2CH1
CH3CH2CH1CH0CH7
CH0 CH1 CH2 CH3 CH4
1417 F22
