22
LTC1417
t
2
t
3
12345678910111213141516
CONVST
EXTCLKIN
t
10
t
dEXTCLKIN
t
5
HOLD
SAMPLE
t
6
t
4
t
9
t
8
BUSY
SCLK
RD
12345678910111213141516 1 2 34
1211109876543210
FILL
ZEROS
D13
Hi-Z
DATA N
Hi-Z
(SAMPLE N)
D
OUT
t
CONV
t
7
1417 F20
D11D12
CAPTURE ON
RISING CLOCK
D13
t
12
t
11
SCLK
V
IL
V
OH
V
OL
D
OUT
CAPTURE ON
FALLING CLOCK
t
LSCLK
t
HSCLK
LTC1417
BUSY
CONVSTCONVST
RD
EXTCLKIN
SCLK
D
OUT
613
12
7
14
9
µP OR DSP
CLKOUT
INT
C0
SCK
MISO
APPLICATIONS INFORMATION
WUU
U
Figure 20. External Conversion Clock Selected. Data Transferred After Conversion
Using an External SCLK. BUSY↑ Indicates End of Conversion
Using an External Conversion Clock and an External
Data Clock. In Figure 20, data is also output after each
conversion is completed and before the next conversion is
started. An external clock is used for the conversion clock
and either another or the same external clock is used for
the SCLK. This mode is identical to Figure 19 except that
an external clock is used for the conversion. This mode
allows the user to synchronize the A/D conversion to an
external clock either to have precise control of the internal
bit test timing or to provide a precise conversion time. As in
Figure 19, this mode works when the SCLK frequency is
very low (less than 30kHz). However, the external conver-
sion clock must be between 30kHz and 9MHz to maintain
accuracy. If more than 16 SCLKs are provided, more zeros
will be filled in after the data word indefinitely. To select the
external conversion clock, apply an external conversion
clock to EXTCLKIN. The external SCLK is applied to SCLK.
RD can be used to gate the external SCLK such that data will
be clocked out only after RD goes low.
