LT8580
19
8580fa
For more information www.linear.com/LT8580
Figure 10. Suggested Component Placement for Boost Topology
(Both DFN and MSOP Packages. Not to Scale). Pin 9 (Exposed
Pad) Must Be Soldered Directly to the Local Ground Plane for
Adequate Thermal Performance. Multiple Vias to Additional
Ground Planes Will Improve Thermal Performance
Figure 11. Suggested Component Placement for SEPIC Topology
(Both DFN And MSOP Packages. Not to Scale). Pin 9 (Exposed
Pad) Must Be Soldered Directly to the Local Ground Plane for
Adequate Thermal Performance. Multiple Vias to Additional
Ground Planes Will Improve Thermal Performance
Figure 12. Suggested Component Placement for Inverting Topology (Both DFN and MSOP Packages. Not to Scale).
Note Cut in Ground Copper at Diode’s Cathode. Pin 9 (Exposed Pad) Must be Soldered Directly to Local Ground Plane
for Adequate Thermal Performance. Multiple Vias to Additional Ground Planes Will Improve Thermal Performance
applicaTions inForMaTion
8580 F11
V
OUT
V
IN
5
6
7
8
9
4
3
2
1
SW
L1
L2
D1
C3
C2
C1
SHDN
SYNC
GND
VIAS TO GROUND
PLANE REQUIRED
TO IMPROVE
THERMAL
PERFORMANCE
8580 F12
V
OUT
V
IN
5
6
7
8
9
4
3
2
1
SW
C1
C2
D1
C3
L1
L2
SHDN
SYNC
GND
VIAS TO GROUND
PLANE REQUIRED
TO IMPROVE
THERMAL
PERFORMANCE
8580 F10
V
OUT
V
IN
C2
L1
C1
D1
5
6
7
8
9
4
3
2
1
SW
SHDN
SYNC
GND
VIAS TO GROUND
PLANE REQUIRED
TO IMPROVE
THERMAL
PERFORMANCE
