LT1952
8
1952f
PI FU CTIO S
UUU
COMP (Pin 1): Output Pin of the Error Amplifier. The error
amplifier is an op amp, allowing various compensation
networks to be connected between the COMP pin and FB
pin for optimum transient response. The voltage on this
pin corresponds to the peak current of the external FET.
Full operating voltage range is between 0.8V and 2.5V
corresponding to 0mV to 220mV at the I
SENSE
pin. For
applications using the 100mV OC pin for over-current
detection, typical operating range for the COMP pin is 0.8V
to 1.6V. For isolated applications where COMP is con-
trolled by an opto-coupler, the COMP pin output drive can
be disabled with FB = V
REF
, reducing the COMP pin current
to (COMP – 0.7)/40k.
FB (Pin 2): Monitors the output voltage via an external
resistor divider and is compared with an internal 1.23V
reference by the error amplifier. FB connected to V
REF
disables error amplifier output.
R
OSC
(Pin 3): A resistor to ground programs the operating
frequency of the IC between 100kHz and 500kHz. Nominal
voltage on the R
OSC
pin is 1.0V.
SYNC (Pin 4): Used to Synchronize the Internal Oscillator
to an External Signal. It is directly logic compatible and can
be driven with any signal between 10% and 90% duty
cycle. If unused, the pin can be left open or connected to
ground.
SS_MAXDC (Pin 5): External resistor divider from V
REF
sets maximum duty cycle clamp (SS_MAXDC = 1.84V,
SD_V
SEC
= 1.32V gives 72% duty cycle). Capacitor on
SS_MAXDC pin in combination with external resistor
divider sets soft-start timing.
V
REF
(Pin 6): The output of an internal 2.5V reference
which supplies control circuitry in the IC. Capable of
sourcing up to 2.5mA drive for external use. Bypass to
ground with a 0.1µF ceramic capacitor.
SD_V
SEC
(Pin 7): The SD_V
SEC
pin, when pulled below its
accurate 1.32V threshold, is used to turn off the IC and
reduce current drain from V
IN.
The SD_V
SEC
pin is con-
nected to system input voltage through a resistor divider
to define undervoltage lockout (UVLO) and to provide a
Volt-Second clamp on the OUT pin. A 10µA pin current
hysteresis allows external programming of UVLO
hysteresis.
GND (Pin 8): Analog Ground.
BLANK (Pin 9): A resistor to ground adjusts the extended
blanking period of the over-current and current sense
amplifier outputs during FET turn on — to prevent false
current limit trip. Increasing the resistor value increases
the blanking period.
I
SENSE
(Pin 10): The Current Sense Input for the Control
Loop. Connect this pin to the sense resistor in the source
of the external power MOSFET. A resistor in series with the
I
SENSE
pin programs slope compensation.
OC (Pin 11): An accurate 100mV threshold, independent
of duty cycle, for over-current detection and trigger of
soft-start. Connect this pin directly to the sense resistor in
the source of the external power MOSFET.
DELAY (Pin 12): A resistor to ground adjusts the delay
period between SOUT rising edge and OUT rising edge.
Used to maximize efficiency in forward converter applica-
tions by adjusting the control timing of secondary side
synchronous rectifier MOSFETs. Increasing the resistor
value increases the delay period.
PGND (Pin 13): Power Ground.
OUT (Pin 14): Drives the Gate of an N-channel MOSFET
between 0V and V
IN
. OUT is actively clamped to 13V.
Active pull-off exists in shutdown (see electrical
specification).
VIN (Pin 15): Input Supply for the Part. It must be closely
decoupled to ground. An internal undervoltage lockout
threshold exists for V
IN
at approximately 14.25V on and
8.75V off.
SOUT (Pin 16): Switched Output in Phase with OUT Pin.
Provides sync signal for control of secondary side FETs in
forward converter applications requiring highly efficient
synchronous rectification. SOUT is actively clamped to
12V. Active pull-off exists in shutdown (see electrical
specification).
